Self-adaptive meta heuristic model for floor planning in very large-scale integration

A.B. Bhavya and S.B. Vinay Kumar

International Journal of Industrial and Systems Engineering, 2025, vol. 51, issue 3, 342-364

Abstract: The process of designing very large scale integrated (VLSI) circuits includes a stage known as floor planning. Floor planning is done to ascertain the relative location of the various modules inside each sub-circuit after the complex circuit is divided into smaller sub-circuits during the partitioning stage. The objectives of this process are to minimise the total chip area covered by the circuit, the amount of dead space in the layout, and the interlinking wire length (WL) among modules. Estimating the placements and forms of the modules is what it is all about. The integrated circuit (IC), which has small feature sizes, a high clock frequency, and high packing density, can dissipate a lot of heat. This work proposes a self-adaptive cat swarm optimisation (SA-CSO) to resolve the floor plan issues. The non-slicing floorplans are regarded by the algorithm as having hard modules with continuous outline restraint. Thus, the area of layout gets reduced.

Keywords: very large scale integrated; VLSI; floorplan; non-slicing plan; dead space; area; SA-CSO algorithm. (search for similar items in EconPapers)
Date: 2025
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