Real-time FPGA-based grayscale image hiding with key masking for secure LSB steganography

Zaid A. Abdulrazzaq (), Fadwa Al Azzo () and Harith G. Ayoub ()

International Journal of Innovative Research and Scientific Studies, 2025, vol. 8, issue 6, 1026-1046

Abstract: The paper presents a novel ZYNQ-FPGA-based real-time grayscale secret image hiding method using a cover RGB image to enhance the security performance of the LSB steganography approach. This work begins with designing a pseudo-random number generator with a 12-bit size using linear feedback shift registers (LFSRs). The two least significant bits (LSBs) are used as indicators for four-position hiding. The key is assumed to be the initial value of the LFSR, exchanged previously between transmitter and receiver over any network. The two position bits extracted through the proposed key masking are resistant to side-channel attacks. All designs are implemented using XSG/SIMULINK environment to verify and validate the results with Xilinx VIVADO tools. The synthesis operation achieved a high frequency of 2.22 GHz and a throughput of 17.7 Gb/s. Statistical analyses include histogram, PSNR, MSE, BER, SSIM, CCR, execution time, frequency, and throughput. Clear structural similarity and processing time contribute to an efficient balance between security and speed performance.

Keywords: FPGA; Information Hiding; Key masking; LFSR; PRNG; XSG. (search for similar items in EconPapers)
Date: 2025
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Persistent link: https://EconPapers.repec.org/RePEc:aac:ijirss:v:8:y:2025:i:6:p:1026-1046:id:9813

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