SEU emulation in industrial SoCs combining microprocessor and FPGA

Igor Villalta, Unai Bidarte, Gómez-Cornejo, Julen, Jiménez, Jaime and Lázaro, Jesús

Reliability Engineering and System Safety, 2018, vol. 170, issue C, 53-63

Abstract: FPGAs (Field-Programmable Gate Array) and FPGA-based SoCs (System-on-chip) are electronic devices which offer high computational performance and low time-to-market for low and medium production volumes. They are gaining popularity in critical sectors, such as automotive, aerospace, avionics and railway, making their reliability evaluation mandatory. FPGAs are notoriously sensitive to SEUs (Single Event Upsets), which are random memory errors provoked by radiation particles. The failure rate of an FPGA varies with the implemented design, depending on the amount of used resources and the implemented redundancy schemes among others. FPGA-based circuits are being used in complex safety-critical engineering systems that are designed in compliance with dependability regulations. This work presents an emulation-based methodology for estimating the failure rate of designs implemented in FPGA SoCs, which is a key data in this scenario.

Keywords: SEU; FPGA; Emulation; Fault injection; FIT (search for similar items in EconPapers)
Date: 2018
References: View references in EconPapers View complete reference list from CitEc
Citations: View citations in EconPapers (5)

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Persistent link: https://EconPapers.repec.org/RePEc:eee:reensy:v:170:y:2018:i:c:p:53-63

DOI: 10.1016/j.ress.2017.09.028

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