A SEU-protected cache memory-based on variable associativity of sets

Hamid Reza Zarandi and Seyed Ghassem Miremadi

Reliability Engineering and System Safety, 2007, vol. 92, issue 11, 1584-1596

Abstract: SRAM cache memories suffer from single event upset (SEU) faults induced by energetic particles such as neutron and alpha particles. To protect these caches, designers often use error detection and correction codes, which typically provide single-bit error detection and even correction. However, these codes have low error detection capability or incur significant performance penalties. In this paper, a protected cache scheme based on the variable associativity of sets is presented. In this scheme, cache space is divided into sets of different sizes with variable tag field lengths. The other remained bits of tags are used for protecting the tag using a new protection code. This leads to protect the cache without compromising performance and area with respect to the similar one, fully associative cache. The scheme provides high SEU detection coverage as well as high performance. Moreover, reliability and mean-time-to-failure (MTTF) equations are derived and estimated. The results obtained from fault injection experiments and several trace files from SPEC2000 reveal that the proposed scheme exhibits a good performance near to fully associative cache but can detect high percent of SEU faults.

Date: 2007
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Persistent link: https://EconPapers.repec.org/RePEc:eee:reensy:v:92:y:2007:i:11:p:1584-1596

DOI: 10.1016/j.ress.2006.10.008

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