A Novel DRAM Cell Structure with Parasitic Storage Capacitance for SoCs on SoI Wafer in 65nm Planar MOS Technology

G. V. Malleshaiah and H. C. Srinivasaiah
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G. V. Malleshaiah: VTU RC, Department of TCE, DSCE Bengaluru
H. C. Srinivasaiah: Research Center, Telecommunication engineering department Dayananda Sagar college of engineering, VTU, Bengaluru

European Journal of Engineering and Technology Research, 2018, vol. 3, issue 10, 58-65

Abstract: A novel 65nm Dynamic Random access memory (DRAM) cell, namely capacitor less RectFET based DRAM cell (CLRDC) is explored in silicon-on-insulator (SoI) wafer for embedded-DRAM (eDRAM) for system-on-chip (SoC), applications with Rectangular FET (RectFET) as its pass-transistor (PT). This CLRDC exploits its parasitic surround buried oxide capacitance (SBC) of SoI-wafer around RectFET (source) for realizing its ‘charge storage capacitance (Cs). For Cs=30fF (femtoFarad) target, it’s found to need an area factor of 4.3µm2 with 5nm thick SoI buried-oxide. This SoI wafer is explored to yield a capacitance density Cbuox=6.91 fF/µm2. The DC parameters of the PT are found to be very sensitive to process anneal temperature (Ta) and so are its DC characteristics too. A 2% increase in the Ta from a nominal 1000oC has resulted in an increase of 30% and 1.1% in the RectFET’s leakage (Idsat-off=I-off) and on-state (Idsat-on=I-on) currents respectively. The CLRDC cell transfer ratio T is also found to be a function of small signal frequency (f), Ta, and source/drain bias voltages Vs/Vd, respectively. And finally the retention characteristics of this CLRDC is again found to be a function of I-off and I-on currents of RectFET, when studied at RectFET’s (drain) supply voltage VDD=1.2V.

Keywords: Capacitorless DRAM; Rectangular FET; Buried Oxide Capacitance; Silicon-on-Insulator; Embedded DRAM; Edram; System-on Chip (search for similar items in EconPapers)
Date: 2018
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Persistent link: https://EconPapers.repec.org/RePEc:epw:ejeng0:v:3:y:2018:i:10:id:60873

DOI: 10.24018/ejeng.2018.3.10.873

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