Hardware co-simulation of 1024-point FFT and it's Implementation, in Simulink, Xilinx Vivado IDE on Zynq-7000 FPGA

K. S. Shashidhara and H. C. Srinivasaiah
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K. S. Shashidhara: VTU RC, Department of TCE, DSCE, Bengaluru, India
H. C. Srinivasaiah: Research Center, Telecommunication engineering department Dayananda Sagar college of engineering, VTU, Bengaluru, India

European Journal of Engineering and Technology Research, 2019, vol. 4, issue 9, 58-64

Abstract: In this paper a 1024-point FFT Algorithm is implemented on Zynq-7000 FPGA device. The design implementation uses Hardware co-simulation in Simulink and Xilinx Vivado environments with Zynq-7000 FPGA target evaluation board using JTAG setup. The power parameter for the configured FFT IP core for 1024 point and the signal source DDS block are estimated. The DDS with both sine and cosine signal outputs enabled, consume a power of 0.277 W, whereas, the 1024 point FFT core consume a power of 0.044 W. Further when 2 DDSs were instanced to generate orthogonal sine and cosine sources for OFDM signals of same frequency 1MHz each, a total of 0.277W power is consumed. When a single DDS core is configured for both sine or cosine signal only configuration by instancing a 1024-point FFT core the total power consumed is 0.268W and 0.267W, respectively, a 1mW higher to cosine case. Further, when 1024 point FFT core power alone is calculated it is found to be 0.044W (or 44mW). When a single DDS is instanced for OFDM signal generation by opting both the sine cosine signals, it consumed a total power of 0.233 W saving a power of 0.044W or 44mW by sine or cosine data re-use from the LUT ROM of DDS. Thus saving a power of 44mW by using data re-use through LUT’s of DDS. This is a significant power saving. In this, hardware co-simulation process, Xilinx system generator tool (Sysgen) is used. This implementation is coded using Verilog HDL, verified on Xilinx Vivado platform on the Zynq-7000 FPGA device. Note that Zynq-7000 is supporting hardware co-simulation, hence the 1024-point FFT has been implemented on this device. The simulation results are captured on Xilinx signal viewer for a proper conclusion.

Keywords: DDS Compiler; FFT-OFDM; LUT ROM; Zynq-7000 FPGA; Xilinx sysgen; Vivado IDE and Hardware co-simulation (search for similar items in EconPapers)
Date: 2019
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Persistent link: https://EconPapers.repec.org/RePEc:epw:ejeng0:v:4:y:2019:i:9:id:61501

DOI: 10.24018/ejeng.2019.4.9.1501

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