Power Quality Improvement in a Cascaded Multilevel Inverter Interfaced Grid Connected System Using a Modified Inductive–Capacitive–Inductive Filter with Reduced Power Loss and Improved Harmonic Attenuation

Meenakshi Jayaraman and Sreedevi Vt
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Meenakshi Jayaraman: School of Electrical Engineering, Vellore Institute of Technology University (VIT University), Chennai 600127, India
Sreedevi Vt: School of Electrical Engineering, Vellore Institute of Technology University (VIT University), Chennai 600127, India

Energies, 2017, vol. 10, issue 11, 1-23

Abstract: Recently, multilevel inverters are more researched due to the advantages they offer over conventional voltage source inverters in grid connected applications. Passive filters are connected at the output of these inverters to produce sinusoidal waveforms with reduced harmonics and to satisfy grid interconnection standard requirements. This work proposes a new passive filter topology for a pulse width modulated five-level cascaded inverter interfaced grid connected system. The proposed passive filter inserts an additional resistance-capacitance branch in parallel to the filter capacitor of the traditional inductive–capacitive–inductive filter in addition to a resistance in series with it to reduce damping power loss. It can attenuate the switching frequency harmonic current components much better than the traditional filter while maintaining the same overall inductance, reduced capacitance and resistance values. The basic parameter design procedure and an approach to discover the parameters of the proposed filter is introduced. Further, a novel methodology using Particle Swarm Optimization (PSO) is recommended to guarantee minimum damping loss while ensuring reduced peak during resonance. In addition, PSO algorithm is newly employed in this work to maximize harmonic attenuation in and around the switching frequency on the premise of allowable values of filter inductance and capacitance. A comparative discussion considering traditional passive filters and the proposed filter is presented and evaluated through experiments conducted on a 110 V, 1 kW five-level grid connected inverter. The modulation algorithm for the multilevel inverter is implemented using a SPARTAN 6-XC6SLX25 Field Programmable Gate Array (FPGA) processor. The analysis shows that the proposed filter not only provides decreased damping power loss but also is capable of providing considerable harmonic ripple reduction in the high frequency band, improved output waveforms and lesser Total Harmonic Distortion (THD) with improved power quality for the multilevel inverter based grid connected system.

Keywords: Pulse Width Modulation (PWM); Field Programmable Gate Array (FPGA); Total Harmonic Distortion (THD); harmonics (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2017
References: View references in EconPapers View complete reference list from CitEc
Citations: View citations in EconPapers (3)

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