A SVPWM to Eliminate Common-Mode Voltage for Multilevel Inverters

Xiongmin Tang, Chengjing Lai, Zheng Liu and Miao Zhang
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Xiongmin Tang: School of automation, Guangdong University of Technology, 510006 Guangzhou, China
Chengjing Lai: School of automation, Guangdong University of Technology, 510006 Guangzhou, China
Zheng Liu: School of Electrical and Information Engineering, Changsha University of Science and Technology, 410004 Changsha, China
Miao Zhang: School of automation, Guangdong University of Technology, 510006 Guangzhou, China

Energies, 2017, vol. 10, issue 5, 1-10

Abstract: This paper presents a new space vector pulse width modulation (SVPWM) to eliminate common-mode voltage (CMV) for multilevel inverters. The proposed SVPWM is performed in a new coordinate system, in which the converter voltage vectors have only integer entries and the absolute coordinate increment between adjacent vectors is equal to 1. The location of the reference vector, detection of the nearest three CMV vectors, and duty cycles of the nearest three CMV vectors are all obtained by simple calculations, no lookup table is needed and the SVPWM is computationally fast. Compared with earlier pulse width modulations (PWMs), the realization of the CMV vectors is very simple, and the CMV of multilevel inverters are limited to zero with any modulation index. Because the SVPWM is independent of the level number of the inverter, the proposed SVPWM is suitable for any level of inverter. This paper also thoroughly compares the proposed SVPWM with prior PWMs. Experimental results are also given in the paper.

Keywords: SVPWM; common-mode voltages; multilevel inverters (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2017
References: View references in EconPapers View complete reference list from CitEc
Citations: View citations in EconPapers (4)

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