A High-Speed Fault Detection, Identification, and Isolation Method for a Last Mile Radial LVDC Distribution Network

Saeed Zaman Jamali, Syed Basit Ali Bukhari, Muhammad Omer Khan, Khawaja Khalid Mehmood, Muhammad Mehdi, Chul-Ho Noh and Chul-Hwan Kim
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Saeed Zaman Jamali: Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea
Syed Basit Ali Bukhari: Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea
Muhammad Omer Khan: Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea
Khawaja Khalid Mehmood: Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea
Muhammad Mehdi: Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea
Chul-Ho Noh: Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea
Chul-Hwan Kim: Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea

Energies, 2018, vol. 11, issue 11, 1-19

Abstract: The day-by-day increase in digital loads draws attention towards the need for an efficient and compatible distribution network. An LVDC distribution network has the capability to fulfill such digital load demands. However, the major challenge of an LVDC distribution network is its vulnerability during a fault. The need for a high-speed fault detection method is inevitable before it can be widely adopted. This paper proposes a new fault detection method which extracts the features of the current during a fault. The proposed fault detection method uses the merits of overcurrent, the first and second derivative of current, and signal processing techniques. Three different features are extracted from a time domain current signal through a sliding window. The extracted features are based upon the root squared zero, second, and fourth order moments. The features are then set with individual thresholds to discriminate low-, high-, and very high-resistance faults. Furthermore, a fault is located through the superimposed power flow. Moreover, this study proposes a new method based on the vector sum of positive and negative pole currents to identify the faulty pole. The proposed scheme is verified by using a modified IEEE 13 node distribution network, which is implemented in Matlab/Simulink. The simulation results confirm the effectiveness of the proposed fault detection and identification method. The simulation results also confirm that a fault having a resistance of 1 m Ω is detected and interrupted within 250 μ s for the test system used in this study.

Keywords: LVDC protection; DC fault detection; DC fault discrimination; DC fault Identification (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2018
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