DC-link Ripple Reduction in a DPWM-Based Two-Level VSI

Anatolii Tcai, Ibrahim Mohd Alsofyani, In-Yong Seo and Kyo-Beum Lee
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Anatolii Tcai: Chair of Power Electronics, Christian-Albrechts-Universität zu Kiel, 2, Kaiserstr, 24143 Kiel, Germany
Ibrahim Mohd Alsofyani: Department of Electrical and Computer Engineering, Ajou University, 206, World cup-ro, Yeongtong-gu Suwon 16499, Korea
In-Yong Seo: KEPCO Research Institute (KEPRI), 55, Jeollyeok-ro, Naju-si, Jeollanam-do 58322, Korea
Kyo-Beum Lee: Department of Electrical and Computer Engineering, Ajou University, 206, World cup-ro, Yeongtong-gu Suwon 16499, Korea

Energies, 2018, vol. 11, issue 11, 1-16

Abstract: This paper proposes a new method to reduce the ripple current of the DC-link capacitor in a two-level voltage source inverter (VSI), with a discontinuous pulse-width modulation (DPWM). In real applications, a capacitor block is very bulky, due to the parallel connection of several capacitors that share the value of the ripple current. Hence, it contributes significantly to the volume and weight of the whole system. Conventional DPWM is used to minimize the amount of switching for the power transistors, therefore, reducing stress and power loss. This leads to increased efficiency and reliability of the system. Nevertheless, the reduction of the DC link ripple current is still not optimal. Therefore, the proposed method introduces a PWM phase-shift technique to provide further reduction of the DC-link ripple current in a DPWM-based VSI. The efficacy of the proposed method is confirmed by simulation and experimental results.

Keywords: dc-link; ripple; capacitor; voltage source inverter (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2018
References: View complete reference list from CitEc
Citations: View citations in EconPapers (3)

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