Hardware in the Loop Real-time Simulation for the Associated Discrete Circuit Modeling Optimization Method of Power Converters
Xizheng Guo,
Jiaqi Yuan,
Yiguo Tang and
Xiaojie You
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Xizheng Guo: Department of Electrical Engineering, Beijing Jiaotong University, Beijing 100044, China
Jiaqi Yuan: Department of Electrical Engineering, Beijing Jiaotong University, Beijing 100044, China
Yiguo Tang: Department of Electrical Engineering, Beijing Jiaotong University, Beijing 100044, China
Xiaojie You: Department of Electrical Engineering, Beijing Jiaotong University, Beijing 100044, China
Energies, 2018, vol. 11, issue 11, 1-14
Abstract:
Due to the complicated circuit topology and high switching frequency, field-programmable gate arrays (FPGA) can stand up to the challenges for the hardware in the loop (HIL) real-time simulation of power electronics converters. The Associated Discrete Circuit (ADC) modeling method, which has a fixed admittance matrix, greatly reduces the computation cost for FPGA. However, the oscillations introduced by the switch-equivalent model reduces the simulation accuracy. In this paper, firstly, a novel algorithm is proposed to determine the optimal discrete-time switch admittance parameter, Gs , which is obtained by minimizing the switching loss. Secondly, the FPGA resource optimization method, in which the simulation time step, bit-length, and model precision are taken into consideration, is presented when the power electronics converter is implemented in FPGA. Finally, the above method is validated on the topology of a three-phase inverter with LC filters. The HIL simulation and practicality experiments verify the effect of FPGA resource optimization and the validity of the ADC modeling method, respectively.
Keywords: hardware in the loop real-time simulation; associated discrete circuit; field-programmable gate arrays resource optimization; time step; bit-length; model precision (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2018
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Citations: View citations in EconPapers (2)
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Persistent link: https://EconPapers.repec.org/RePEc:gam:jeners:v:11:y:2018:i:11:p:3237-:d:184551
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