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Secure Protocol and IP Core for Configuration of Networking Hardware IPs in the Smart Grid

Marcelo Urbina, Naiara Moreira, Mikel Rodriguez, Tatiana Acosta, Jesús Lázaro and Armando Astarloa
Additional contact information
Marcelo Urbina: Departamento de Eléctrica y Electrónica, Universidad de las Fuerzas Armadas ESPE, 171-5-231B Sangolquí, Ecuador
Naiara Moreira: Departamento de Tecnología Electrónica, Universidad del País Vasco/Euskal Herriko Unibertsitatea (UPV/EHU), 48013 Bilbao, Spain
Mikel Rodriguez: System-on-Chip Engineering, Ed Udondo Planta 6, Ribera de Axpe 50, 48950 Erandio, Spain
Tatiana Acosta: Departamento de Eléctrica y Electrónica, Universidad de las Fuerzas Armadas ESPE, 171-5-231B Sangolquí, Ecuador
Jesús Lázaro: Departamento de Tecnología Electrónica, Universidad del País Vasco/Euskal Herriko Unibertsitatea (UPV/EHU), 48013 Bilbao, Spain
Armando Astarloa: Departamento de Tecnología Electrónica, Universidad del País Vasco/Euskal Herriko Unibertsitatea (UPV/EHU), 48013 Bilbao, Spain

Energies, 2018, vol. 11, issue 3, 1-13

Abstract: Nowadays, the incorporation and constant evolution of communication networks in the electricity sector have given rise to the so-called Smart Grid, which is why it is necessary to have devices that are capable of managing new communication protocols, guaranteeing the strict requirements of processing required by the electricity sector. In this context, intelligent electronic devices (IEDs) with network architectures are currently available to meet the communication, real-time processing and interoperability requirements of the Smart Grid. The new generation IEDs include an Field Programmable Gate Array (FPGA), to support specialized networking switching architectures for the electric sector, as the IEEE 1588-aware High-availability Seamless Redundancy/Parallel Redundancy Protocol (HSR/PRP). Another advantage to using an FPGA is the ability to update or reconfigure the design to support new requirements that are being raised to the standards (IEC 61850). The update of the architecture implemented in the FPGA can be done remotely, but it is necessary to establish a cyber security mechanism since the communication link generates vulnerability in the case the attacker gains physical access to the network. The research presented in this paper proposes a secure protocol and Intellectual Property (IP) core for configuring and monitoring the networking IPs implemented in a Field Programmable Gate Array (FPGA). The FPGA based implementation proposed overcomes this issue using a light Layer-2 protocol fully implemented on hardware and protected by strong cryptographic algorithms (AES-GCM), defined in the IEC 61850-90-5 standard. The proposed secure protocol and IP core are applicable in any field where remote configuration over Ethernet is required for IP cores in FPGAs. In this paper, the proposal is validated in communications hardware for Smart Grids.

Keywords: cyber-security; Configuration Over Ethernet secure (COEsec); Field Programmable Gate Array (FPGA); High-availability Seamless Redundancy (HSR); IEC 61850; Industrial communication; Smart Grid; Substation Automation Systems (SAS); cryptography (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2018
References: View complete reference list from CitEc
Citations: View citations in EconPapers (1)

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