Single Inductor-Multiple Output DPWM DC-DC Boost Converter with a High Efficiency and Small Area

Young Jun Park, Zaffar Hayat Nawaz Khan, Seong Jin Oh, Byeong Gi Jang, Nabeel Ahmad, Danial Khan, Hamed Abbasizadeh, Syed Adil Ali Shah, Young Gun Pu, Keum Cheol Hwang, Youngoo Yang, Minjae Lee and Kang Yoon Lee
Additional contact information
Young Jun Park: College of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, Korea
Zaffar Hayat Nawaz Khan: College of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, Korea
Seong Jin Oh: College of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, Korea
Byeong Gi Jang: College of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, Korea
Nabeel Ahmad: College of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, Korea
Danial Khan: College of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, Korea
Hamed Abbasizadeh: College of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, Korea
Syed Adil Ali Shah: College of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, Korea
Young Gun Pu: College of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, Korea
Keum Cheol Hwang: College of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, Korea
Youngoo Yang: College of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, Korea
Minjae Lee: School of Electrical Engineering and Computer Science, Gwangju Institute of Science and Technology, Gwangju 61005, Korea
Kang Yoon Lee: College of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, Korea

Energies, 2018, vol. 11, issue 4, 1-13

Abstract: In this paper, a small-area and high-efficiency single-inductor multiple output (SIMO) boost converter with digital pulse-width modulation (DPWM) is proposed. The DPWM comprises a delay line using interlaced hysteresis delay cells (IHDCs) that occupy a small area while consuming a low power amount. These proposed IHDCs are applied to replace the conventional delay cells of the prior works for both the power and area reductions. Regarding the DC-DC converter, this technique comprises fewer digital blocks in the feedback path compared with the conventional DC-DC converter, and the DPWM architecture uses IHDCs. The purpose of the digital limiter block is to concede some helpful code for the DPWM. The IHDC topology used for delay in DPWM is of the simplest architecture. The high-side power switch gate drivers need individual phases which are generated by phase control. The Complementary Metal Oxide Semiconductor (CMOS)-fabrication process is 55 nm, with a standard supply voltage of 1.8 V and outputs of 2.2 and 2.4 V. The chip area is approximately 170 × 190 µm and its efficiency is 94.4%.

Keywords: DC-DC converter; digital pulse width modulation; interlaced hysteresis delay cells (IHDCs) (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2018
References: View complete reference list from CitEc
Citations: View citations in EconPapers (2)

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