A Simple Multilevel Space Vector Modulation Technique and MATLAB System Generator Built FPGA Implementation for Three-Level Neutral-Point Clamped Inverter

P. Madasamy, R. K. Pongiannan, Sekar Ravichandran, Sanjeevikumar Padmanaban, Bharatiraja Chokkalingam, Eklas Hossain and Yusuff Adedayo
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P. Madasamy: Department of Electrical and Electronics Engineering, Alagappa Chettiar college of Engineering and Technology, Karaikudi 630003, India
R. K. Pongiannan: Department of Electrical and Electronics Engineering, SRM Institute of Science and Technology, Chennai 603203, India
Sekar Ravichandran: Department of Electrical and Electronics Engineering, Sreenidhi Institute of Science and Technology, Hyderabad, Telangana 501301, India
Sanjeevikumar Padmanaban: Department of Energy Technology, Aalborg University, 6700 Esbjerg, Denmark
Bharatiraja Chokkalingam: Department of Electrical and Electronics Engineering, SRM Institute of Science and Technology, Chennai 603203, India
Eklas Hossain: Oregon Renewable Energy Center (OREC), Department of Electrical Engineering & Renewable Energy, Oregon Tech, Klamath Falls, OR 97601, USA
Yusuff Adedayo: Department of Electrical Engineering, University of South Africa, Pretoria 1709, South Africa

Energies, 2019, vol. 12, issue 22, 1-24

Abstract: The pulse width modulation (PWM) is an important segment in power electronic inverters and multilevel inverters (MLIs) design. The space vector modulation (SVM) methods own distinct advantages over other PWM methods. However, MLI SVM has involved more mathematics in their executions. Hence, the digital signal processors (DSPs) or field programmable gate arrays (FPGAs) based digital implementations are highly preferred for MLI SVM realizations, which require exceptional properties. The conventional MLI SVMs use complex mathematical functions to solve their internal functions to identify the space vector diagram (SVD) sub-triangle and over modulation boundary switching on-times. Particularly these are the changes in the position of reference vector with respect to their sub-triangle positions involving higher mathematical functions. This paper proposes a simplified three-level MLI SVM that reduces the sub-triangle and over modulation switching on-time calculations with reduced mathematical functions. The proposed MLI SVM is derived based on two-level SVM without changing the reference vector position, unlike the traditional approaches. This helps in extending the SVM for any n-level inverter with additional LUTs. The detailed theoretical study, MATLAB-Simulink system generator simulations and Xilinx FPGA family SPARTAN-III-3A based experimental implementations are done with three-level neutral point MLI fed induction motor drive. The theoretical design, analysis, and experimentation results validate the advantages of the proposed PWM design and its implementation. In addition, the proposed implementation is executed from the MATLAB Xilinx system generator directly into target FPGA, which makes it faithful, efficient and minimizes the time spent.

Keywords: pulse width modulation (PWM); multilevel inverter (MLI); space vector modulation (SVM); field programmable gate array (FPGA) (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2019
References: View references in EconPapers View complete reference list from CitEc
Citations: View citations in EconPapers (2)

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