SPOF—Slave Powerlink on FPGA for Smart Sensors and Actuators Interfacing for Industry 4.0 Applications

Giacomo Valente, Vittoriano Muttillo, Mirco Muttillo, Gianluca Barile, Alfiero Leoni, Walter Tiberti and Luigi Pomante
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Giacomo Valente: Dipartimento di Ingegneria e Scienze dell’Informazione e Matematica, Università degli Studi dell’Aquila, 67100 L’Aquila, Italy
Vittoriano Muttillo: Dipartimento di Ingegneria e Scienze dell’Informazione e Matematica, Università degli Studi dell’Aquila, 67100 L’Aquila, Italy
Mirco Muttillo: Dipartimento di Ingegneria Industriale e dell’Informazione e di Economia, Università degli Studi dell’Aquila, 67100 L’Aquila, Italy
Gianluca Barile: Dipartimento di Ingegneria Industriale e dell’Informazione e di Economia, Università degli Studi dell’Aquila, 67100 L’Aquila, Italy
Alfiero Leoni: Dipartimento di Ingegneria Industriale e dell’Informazione e di Economia, Università degli Studi dell’Aquila, 67100 L’Aquila, Italy
Walter Tiberti: Dipartimento di Ingegneria e Scienze dell’Informazione e Matematica, Università degli Studi dell’Aquila, 67100 L’Aquila, Italy
Luigi Pomante: Dipartimento di Ingegneria e Scienze dell’Informazione e Matematica, Università degli Studi dell’Aquila, 67100 L’Aquila, Italy

Energies, 2019, vol. 12, issue 9, 1-13

Abstract: We here present a new PLC-POWERLINK industrial solution for Industry 4.0 applications. The proposed solution provides the capability to separate the sensing functionality from the PLC-side, in demand for the reconfigurable FPGA implementation. In particular, we here provide a framework that supports the interfacing between the POWERLINK protocol and commonly used standards, such as I2C, SPI, and UART. This has been obtained by using a framework built around a soft IP-core Application Processor, which manages the interfacing with several POWERLINK slaves, able to support the data exchange with the POWERLINK Communication Processor. A practical application example and related implementation details are presented in the paper.

Keywords: POWERLINK; PLC; multi-core; FPGA; sensor interfacing (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2019
References: View references in EconPapers View complete reference list from CitEc
Citations: View citations in EconPapers (2)

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