Experimental Evaluation of a Control System Based on a Dual-DSP Architecture for a Unified Power Quality Conditioner

Luís Monteiro, Bruno Exposto, Gabriel Pinto, Vitor Monteiro, Maurício Aredes and João L. Afonso
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Luís Monteiro: Department of Electronics and Communications, Rio de Janeiro State University, Rio de Janeiro—RJ 20550-900, Brazil
Bruno Exposto: Department of Industrial Electronics, University of Minho, 4800-058 Guimarães, Portugal
Gabriel Pinto: Department of Industrial Electronics, University of Minho, 4800-058 Guimarães, Portugal
Vitor Monteiro: Department of Industrial Electronics, University of Minho, 4800-058 Guimarães, Portugal
Maurício Aredes: Department of Electrical Engineering, Federal University of Rio de Janeiro, Rio de Janeiro—RJ 21941-901, Brazil
João L. Afonso: Department of Industrial Electronics, University of Minho, 4800-058 Guimarães, Portugal

Energies, 2019, vol. 12, issue 9, 1-16

Abstract: An experimental evaluation of a digital control system based on a dual Digital Signal Processor (DSP) architecture is proposed for a three phase Unified Power Quality Conditioner (UPQC). A classical UQPC is constituted by two power conditioners, connected in series and shunted with the power grid, and sharing a common DC-link. In a smart grid scenario of operation, a UPQC will be fundamental for compensating power quality problems, also contributing to improving the efficiency of the electrical grids from a global perspective. The UPQC operation requires a bidirectional energy transfer between the two power conditioners, however, respecting some constraints, they can be controlled independently. In order to take advantage of this characteristic, the control algorithms can be executed on two independent DSPs, without any communication between them and maintaining the operational characteristics of the UPQC. Comparing with the classical control architecture based on a single DSP, with the proposed dual DSP architecture, the computational effort of each DSP is decreased of about 35%, allowing to increase the sampling rate. Therefore, the main advantages of the proposed approach are the minimization of delays caused by the processing time, which are very common in digital control systems, as well as the increment of the UPQC performance. Along the paper, detailed analysis of the processing speed and memory requirements to implement the UPQC control algorithms in both DSPs is presented. The paper also presents a set of detailed experimental results, obtained with a developed 5 kVA laboratory prototype of UPQC, which was used to evaluate the performance of the proposed dual DSP architecture.

Keywords: DSP; UPQC; power quality; digital control; real-time systems (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2019
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