Reliability Characterization of Gallium Nitride MIS-HEMT Based Cascode Devices for Power Electronic Applications

Surya Elangovan, Stone Cheng and Edward Yi Chang
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Surya Elangovan: Department of Mechanical Engineering, National Chiao Tung University, Hsinchu City 30010, Taiwan
Stone Cheng: Department of Mechanical Engineering, National Chiao Tung University, Hsinchu City 30010, Taiwan
Edward Yi Chang: Department of Material Science and Engineering, National Chiao Tung University, Hsinchu City 30010, Taiwan

Energies, 2020, vol. 13, issue 10, 1-11

Abstract: We present a detailed study of dynamic switching instability and static reliability of a Gallium Nitride (GaN) Metal-Insulator-Semiconductor High-Electron-Mobility-Transistor (MIS-HEMT) based cascode switch under off-state (negative bias) Gate bias stress (V GS, OFF ). We have investigated drain channel current (I DS, Max ) collapse/degradation and turn-on and rise-time (t R ) delay, on-state resistance (R DS-ON ) and maximum transconductance (G m, max ) degradation and threshold voltage (V TH ) shift for pulsed and prolonged off-state gate bias stress V GS, OFF . We have found that as stress voltage magnitude and stress duration increases, similarly I DS, Max and R DS-ON degradation, V TH shift and turn-on/rise time (t R ) delay, and G m, max degradation increases. In a pulsed off-state V GS, OFF stress experiment, the device instabilities and degradation with electron trapping effects are studied through two regimes of stress voltages. Under low stress, V TH shift, I DS collapse, R DS-ON degradation has very minimal changes, which is a result of a recoverable surface state trapping effect. For high-stress voltages, there is an increased and permanent V TH shift and high I DS, Max and R DS-ON degradation in pulsed V GS, Stress and increased rise-time and turn-on delay. In addition to this, a positive V TH shift and G m, max degradation were observed in prolonged stress experiments for selected high-stress voltages, which is consistent with interface state generation. These findings provide a path to understand the failure mechanisms under room temperature and also to accelerate the developments of emerging GaN cascode technologies.

Keywords: gallium nitride HEMT; cascode configuration; off-state gate bias stress; device degradation; failure mechanisms; electronic trapping effects (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2020
References: View complete reference list from CitEc
Citations: View citations in EconPapers (3)

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