Thermo-Fluidic Characterizations of Multi-Port Compact Thermal Model of Ball-Grid-Array Electronic Package

Valentin Bissuel, Frédéric Joly, Eric Monier-Vinard, Alain Neveu and Olivier Daniel
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Valentin Bissuel: Thales Corporate Engineering, 19-21 Avenue Morane Saulnier, 78140 Vélizy-Villacoublay, France
Frédéric Joly: LMEE, Université d’Evry, Université Paris-Saclay, 91020 Evry, France
Eric Monier-Vinard: Thales Corporate Engineering, 19-21 Avenue Morane Saulnier, 78140 Vélizy-Villacoublay, France
Alain Neveu: LMEE, Université d’Evry, Université Paris-Saclay, 91020 Evry, France
Olivier Daniel: Thales Corporate Engineering, 19-21 Avenue Morane Saulnier, 78140 Vélizy-Villacoublay, France

Energies, 2020, vol. 13, issue 11, 1-17

Abstract: The concept of a single-input/multi-output thermal network was proposed by the Development of Libraries of Physical models for an Integrated design environment (DELPHI) consortium more than twenty years ago. The present work highlights the recent improvements made to efficiently derive a low-computing-effort model from a fully detailed numerical model and to characterize its performances. The temperature predictions of a deduced ball-grid-array (BGA) dynamic compact thermal model are compared to those of a realistic three-dimensional representation, including the large set of internal copper traces, as well as its board structure, which has been validated by experiment. The current study discloses a method for creating an amalgam reduced-order modal model (AROMM) for that electronic component family that allows the preservation of the geometry integrity and shortening scenarios computation. Typically, the AROMM method reduces by a factor of 600 the computation time needed to obtain the solution while keeping the error on the maximum temperature below 2%. Then, a meta-heuristic optimization is run to derive a more practical low-order resistor capacitor model that enables a thermo-fluidic analysis at the board level. Based on the calibrated numerical model, a novel AROMM method was investigated in order to address the chip behavior submitted to multiple heat sources. The first results highlight the capability to enforce a non-uniform power distribution on the upper surface of the silicon chip. Thus, the chip design layout can be analyzed and optimized to prevent thermal and reliability issues.

Keywords: BCI-DCTM; ROM; modal approach; BGA; experimental validation (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2020
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