Influence of MOSFET Parasitic Capacitance on the Operation of Interleaved ZVS Boost Converters

Piotr Zimoch, Marcin Kasprzak and Kamil Kierepka
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Piotr Zimoch: Department of Power Electronics, Electrical Drive and Robotics, Silesian University of Technology; 44100, Gliwice, Poland
Marcin Kasprzak: Department of Power Electronics, Electrical Drive and Robotics, Silesian University of Technology; 44100, Gliwice, Poland
Kamil Kierepka: Department of Power Electronics, Electrical Drive and Robotics, Silesian University of Technology; 44100, Gliwice, Poland

Energies, 2020, vol. 13, issue 22, 1-17

Abstract: Interleaved zero-voltage switching boost converters have been known for over 20 years. However, the influence of parasitic capacitance of transistors has not been described. In this paper the converter is analyzed and the equation for voltage ratio is derived for any number of converter phases. First a general description of the topology, including main voltage and current waveforms, is provided. Subsequently the converter is analyzed and conditions for soft switching are derived. Next the analysis results are compared to measurements of an experimental converter setup. Discrepancies are identified and the influence of parasitic capacitance is analyzed. By considering the parasitic capacitance the difference between experimental and analytical results of voltage ratio is reduced from 0.2 to less than 0.05.

Keywords: zero-voltage switching (ZVS); quasi-resonant converters; boost converter; output capacitance (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2020
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