Fault Location Method Using Phasor Measurement Units and Short Circuit Analysis for Power Distribution Networks

Ji-Song Hong, Gi-Do Sim, Joon-Ho Choi, Seon-Ju Ahn and Sang-Yun Yun
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Ji-Song Hong: Department of Electrical Engineering, Chonnam National University 77, Yongbong-Ro, Buk-Gu, Gwangju 61186, Korea
Gi-Do Sim: Department of Electrical Engineering, Chonnam National University 77, Yongbong-Ro, Buk-Gu, Gwangju 61186, Korea
Joon-Ho Choi: Department of Electrical Engineering, Chonnam National University 77, Yongbong-Ro, Buk-Gu, Gwangju 61186, Korea
Seon-Ju Ahn: Department of Electrical Engineering, Chonnam National University 77, Yongbong-Ro, Buk-Gu, Gwangju 61186, Korea
Sang-Yun Yun: Department of Electrical Engineering, Chonnam National University 77, Yongbong-Ro, Buk-Gu, Gwangju 61186, Korea

Energies, 2020, vol. 13, issue 5, 1-23

Abstract: This paper proposes a fault location method for power distribution networks using phasor measurement units (PMU) and short circuit analysis. In order to improve the problems of the existing studies, we focused on several approaches as follows. First, in order to minimize the number of PMU installations, a fault location estimation of lateral feeders through short circuit analysis was presented. Second, unbalanced faults and impacts of photovoltaic (PV) were considered. The proposed method consists of two stages. In Stage 1, the fault location was estimated for the main feeder using PMU installed at the start and end points of the main feeder. Symmetrical components of voltage and current variation were calculated by considering the impact of PVs interconnected to the lateral feeders. If the result of Stage 1 indicated a connection section of lateral feeder on the main feeder, Stage 2 would be performed. In Stage 2, the fault location was estimated for the lateral feeder by comparing the results of the short circuit analysis and measurements of PMUs. The short circuit analysis was based on an unbalanced power flow that considered dynamic characteristics of the PV inverter. The proposed method was verified through various fault situations in a test system. For the applicability of the proposed algorithm to the actual system, a noise test was also performed.

Keywords: fault location estimation; phasor measurement unit; 2-stage method; FLISR; short circuit analysis; unbalanced power flow (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2020
References: View references in EconPapers View complete reference list from CitEc
Citations: View citations in EconPapers (1)

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