AHEAD: Automatic Holistic Energy-Aware Design Methodology for MLP Neural Network Hardware Generation in Proactive BMI Edge Devices

Nan-Sheng Huang, Yi-Chung Chen, Jørgen Christian Larsen and Poramate Manoonpong
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Nan-Sheng Huang: Embodied AI and Neurorobotics Laboratory, SDU Biorobotics, Mærsk Mc-Kinney Møller Institute, University of Southern Denmark, 5230 Odense, Denmark
Yi-Chung Chen: Department of Electrical and Computer Engineering, Tennessee State University, Nashville, TN 37209, USA
Jørgen Christian Larsen: Embodied AI and Neurorobotics Laboratory, SDU Biorobotics, Mærsk Mc-Kinney Møller Institute, University of Southern Denmark, 5230 Odense, Denmark
Poramate Manoonpong: Embodied AI and Neurorobotics Laboratory, SDU Biorobotics, Mærsk Mc-Kinney Møller Institute, University of Southern Denmark, 5230 Odense, Denmark

Energies, 2020, vol. 13, issue 9, 1-20

Abstract: The prediction of a high-level cognitive function based on a proactive brain–machine interface (BMI) control edge device is an emerging technology for improving the quality of life for disabled people. However, maintaining the stability of multiunit neural recordings is made difficult by the nonstationary nature of neurons and can affect the overall performance of proactive BMI control. Thus, it requires regular recalibration to retrain a neural network decoder for proactive control. However, retraining may lead to changes in the network parameters, such as the network topology. In terms of the hardware implementation of the neural decoder for real-time and low-power processing, it takes time to modify or redesign the hardware accelerator. Consequently, handling the engineering change of the low-power hardware design requires substantial human resources and time. To address this design challenge, this work proposes AHEAD: an automatic holistic energy-aware design methodology for multilayer perceptron (MLP) neural network hardware generation in proactive BMI edge devices. By taking a holistic analysis of the proactive BMI design flow, the approach makes judicious use of the intelligent bit-width identification (BWID) and configurable hardware generation, which autonomously integrate to generate the low-power hardware decoder. The proposed AHEAD methodology begins with the trained MLP parameters and golden datasets and produces an efficient hardware design in terms of performance, power, and area (PPA) with the least loss of accuracy. The results show that the proposed methodology is up to a 4X faster in performance, 3X lower in terms of power consumption, and achieves a 5X reduction in area resources, with exact accuracy, compared to floating-point and half-floating-point design on a field-programmable gate array (FPGA), which makes it a promising design methodology for proactive BMI edge devices.

Keywords: neural network; edge device; field-programmable gate array; hardware acceleration; high-level synthesis; energy-aware design; brain–machine interface (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2020
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