A New Multilevel Inverter Topology with Reduced DC Sources

Muhyaddin Rawa, Prem P, Jagabar Sathik Mohamed Ali, Marif Daula Siddique, Saad Mekhilef, Addy Wahyudie, Mehdi Seyedmahmoudian and Alex Stojcevski
Additional contact information
Muhyaddin Rawa: Department of Electrical and Computer Engineering, King Abdulaziz University, Jeddah 21589, Saudi Arabia
Prem P: Switchgear Electromechanical, Chennai 600082, India
Jagabar Sathik Mohamed Ali: Department of Electrical and Electronics Engineering, SRM Institute of Science and Technology, Kattankulathur Campus, Kattankulathur 603203, India
Marif Daula Siddique: Power Electronics and Renewable Energy Research Laboratory, Department of Electrical Engineering, University of Malaya, Kuala Lumpur 50603, Malaysia
Saad Mekhilef: Department of Electrical and Computer Engineering, King Abdulaziz University, Jeddah 21589, Saudi Arabia
Addy Wahyudie: Electrical Engineering Department, United Arab Emirates University, Al Ain 15551, United Arab Emirates
Mehdi Seyedmahmoudian: School of Software and Electrical Engineering, Faculty of Science, Engineering and Technology, Swinburne University of Technology, Victoria, VIC 3122, Australia
Alex Stojcevski: School of Software and Electrical Engineering, Faculty of Science, Engineering and Technology, Swinburne University of Technology, Victoria, VIC 3122, Australia

Energies, 2021, vol. 14, issue 15, 1-21

Abstract: The component count for the multilevel inverter has been a research topic for the last few decades. The higher number of power semiconductor devices and sources leads to a higher power loss with the complex control requirement. A new multilevel inverter topology employing the concept of half-Bridge modules is suggested in this paper. It requires a lower number of dc sources and power components. The inverter is controlled using a fundamental frequency switching scheme. With the basic unit being able to produce 13 level voltage waveforms with three dc voltage sources, higher-level inverter configuration has also been discussed in the paper. The performance of the topology is analyzed in the aspects of circuit parameters and found better when compared to similar topologies proposed in recent literature. The comparison provided in the paper set the benchmark of the proposed topology in terms of lower component requirements. The topology is also optimized with two voltage fixing algorithms for maximizing the number of levels for the given number of IGBTs, drivers and dc sources, and the observations are presented. The efficiency analysis gives the peak efficiency as 98.5%. The simulations were carried out using the PLECS software tool and validated using a prototype rated at 500 W. The results with several test conditions have been reported and discussed in the paper.

Keywords: dc/ac power conversion; asymmetrical; multilevel inverter; reduced switch count; pulse width modulation; power converter (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2021
References: View references in EconPapers View complete reference list from CitEc
Citations: View citations in EconPapers (3)

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