Optimized Modulation Method for Common-Mode Voltage Reduction in H7 Inverter

Belete Belayneh Negesse, Chang-Hwan Park, Seung-Hwan Lee, Seon-Woong Hwang and Jang-Mok Kim
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Belete Belayneh Negesse: Department of Electrical and Computer Engineering, Pusan National University, 2 Busandaehak-ro 63beon-gil, Geumjeong-gu, Busan 46241, Korea
Chang-Hwan Park: Department of Electrical and Computer Engineering, Pusan National University, 2 Busandaehak-ro 63beon-gil, Geumjeong-gu, Busan 46241, Korea
Seung-Hwan Lee: Living Appliance Control Research Division of LG Electronics, 84 Wanam-ro, Seongsan-gu, Changwon 51554, Korea
Seon-Woong Hwang: Department of Electrical and Computer Engineering, Pusan National University, 2 Busandaehak-ro 63beon-gil, Geumjeong-gu, Busan 46241, Korea
Jang-Mok Kim: Department of Electrical and Computer Engineering, Pusan National University, 2 Busandaehak-ro 63beon-gil, Geumjeong-gu, Busan 46241, Korea

Energies, 2021, vol. 14, issue 19, 1-17

Abstract: The three-phase H7 inverter topology installs an additional power semiconductor switch to the positive or negative node of the DC-link for reducing the common-mode voltage (CMV) by disconnecting the inverter from the DC source during the zero-voltage vectors. The conventional CMV reduction method for the three-phase H7 inverter uses modified discontinuous pulse width modulation (MDPWM) and generates a switching signal for the additional switch using logical operations. However, the conventional method is unable to eliminate the CMV for the entire dwell time of the zero-voltage vectors. It only has the effect of reducing the CMV in a limited area of the space vector where the V 7 zero voltage vector is applied. Therefore, this paper proposes an optimized modulation method that can reduce the CMV during the entire dwell time of zero-voltage vectors. The proposed method moves the switching patterns by adding an offset voltage to guarantee that only one kind of zero-voltage vector, V 7 , is applied in the system. It then turns off the seventh switch only during the zero-voltage vector to disconnect the inverter from the DC source. As a result, the CMV and the leakage current are attenuated for the entire dwell time of the zero-voltage vector. Simulation and experimental results confirm the validity of the proposed method.

Keywords: common-mode voltage; zero-voltage vector; H7 inverter; PMSM (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2021
References: View complete reference list from CitEc
Citations: View citations in EconPapers (1)

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