A Multilevel Inverter Topology Using Diode Half-Bridge Circuit with Reduced Power Component

Jagabar Sathik, Shady H. E. Abdel Aleem, Rasoul Shalchi Alishah, Dhafer Almakhles, Kent Bertilsson, Mahajan Sagar Bhaskar, George Fernandez Savier and Karthikeyan Dhandapani
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Jagabar Sathik: Renewable Energy Laboratory, Prince Sultan University, Riyadh 11586, Saudi Arabia
Shady H. E. Abdel Aleem: Department of Electrical Engineering, Valley Higher Institute of Engineering and Technology, Science Valley Academy, Qalyubia 44971, Egypt
Rasoul Shalchi Alishah: Department of Electronics, Mid-Sweden University, Holmgatan 10, 851 70 Sundsvall, Sweden
Dhafer Almakhles: Renewable Energy Laboratory, Prince Sultan University, Riyadh 11586, Saudi Arabia
Kent Bertilsson: Department of Electronics, Mid-Sweden University, Holmgatan 10, 851 70 Sundsvall, Sweden
Mahajan Sagar Bhaskar: Renewable Energy Laboratory, Prince Sultan University, Riyadh 11586, Saudi Arabia
George Fernandez Savier: Department of Electrical and Electronics Engineering, SRM Institute of Science and Technology, Kattankulathur Campus, Kattankulathur 603203, India
Karthikeyan Dhandapani: Department of Electrical and Electronics Engineering, SRM Institute of Science and Technology, Kattankulathur Campus, Kattankulathur 603203, India

Energies, 2021, vol. 14, issue 21, 1-21

Abstract: This paper presents a new multilevel converter with a reduced number of power components for medium voltage applications. Both symmetric and asymmetric structures of the presented multilevel converter are proposed. The symmetric topology requires equal dc source values, whereas the asymmetric topology uses minimum switch count. However, both structures suffer from high blocking voltage across the switches. To reduce the blocking voltage on switches, an optimal topology is presented and analyzed for the selection of the minimum number of switches and dc sources, while maintaining a low blocking voltage across the switches. A comparative analysis with recently published topologies was performed. The simulation results, as well as the comparative analysis, validated the robustness and effectiveness of the proposed topology in terms of the reduced power loss, lowered number of components, and cost. Furthermore, in addition to the simulation results, the performance of the proposed topology was verified using experimental results of 9, 17, and 25 levels.

Keywords: multilevel inverter; diode half-bridge circuit; power devices; asymmetric inverter; symmetric inverter (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2021
References: View references in EconPapers View complete reference list from CitEc
Citations: View citations in EconPapers (2)

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