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Technical Assessment of Hybrid HVDC Circuit Breaker Components under M-HVDC Faults

Saqib Khalid, Ali Raza, Umar Alqasemi, Nebras Sobahi, Muhammad Zain Yousaf, Ghulam Abbas and Mohsin Jamil
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Saqib Khalid: Department of Electrical Engineering, The University of Lahore, Lahore 54000, Pakistan
Ali Raza: Department of Electrical Engineering, University of Engineering and Technology, Lahore 54000, Pakistan
Umar Alqasemi: Department of Electrical and Computer Engineering, King Abdulaziz University, Jeddah 21589, Saudi Arabia
Nebras Sobahi: Department of Electrical and Computer Engineering, King Abdulaziz University, Jeddah 21589, Saudi Arabia
Muhammad Zain Yousaf: School of Electrical Engineering, Guangxi University, Nanning 530600, China
Ghulam Abbas: Department of Electrical Engineering, The University of Lahore, Lahore 54000, Pakistan
Mohsin Jamil: Faculty of Engineering and Applied Science, Memorial University of Newfoundland, St. John’s, NL A1B 3X5, Canada

Energies, 2021, vol. 14, issue 23, 1-16

Abstract: One of the technical challenges that needs to be addressed for the future of the multi-terminal high voltage direct current (M-HVDC) grid is DC fault isolation. In this regard, HVDC circuit breakers (DCCBs), particularly hybrid circuit breakers (H-DCCBs), are paramount. The H-DCCB, proposed by the ABB, has the potential to ensure a reliable and safer grid operation, mainly due to its millisecond-level current interruption capability and lower on-state losses as compared to electromechanical and solid-state based DCCBs. This paper aims to study and evaluate the operational parameters, e.g., electrical, and thermal stresses on the IGBT valves and energy absorbed by the surge arrestors within H-DCCB during different DC fault scenarios. A comprehensive set of modeling requirements matching with operational conditions are developed. A meshed four-terminal HVDC test bench consisting of twelve H-DCCBs is designed in PSCAD/EMTDC to study the impacts of the M-HVDC grid on the operational parameters of H-DCCB. Thus, the system under study is tested for different current interruption scenarios under a (i) low impedance fault current and (ii) high impedance fault current. Both grid-level and self-level protection strategies are implemented for each type of DC fault.

Keywords: electrical and thermal stresses; hybrid HVDC circuit breaker; multi-terminal HVDC transmission systems; HVDC grid protection (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2021
References: View references in EconPapers View complete reference list from CitEc
Citations: View citations in EconPapers (3)

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