Optimization of a Gate Distribution Layout to Compensate the Current Imbalance Generated by the 3D Geometry of a Railway Inverter

Andressa Nakahata-Medrado, Jean-Luc Schanen, Jean-Michel Guichon, Pierre-Olivier Jeannin, Emmanuel Batista and Guillaume Desportes
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Andressa Nakahata-Medrado: G2ELab, University Grenoble Alpes, 21 Av des Martyrs, 38000 Grenoble, France
Jean-Luc Schanen: G2ELab, University Grenoble Alpes, 21 Av des Martyrs, 38000 Grenoble, France
Jean-Michel Guichon: G2ELab, University Grenoble Alpes, 21 Av des Martyrs, 38000 Grenoble, France
Pierre-Olivier Jeannin: G2ELab, University Grenoble Alpes, 21 Av des Martyrs, 38000 Grenoble, France
Emmanuel Batista: Alstom Transport, 21 rue Dr Guinier, 65600 Semeac, France
Guillaume Desportes: Alstom Transport, 21 rue Dr Guinier, 65600 Semeac, France

Energies, 2021, vol. 14, issue 7, 1-18

Abstract: The impact of the stray inductances originated from interconnects in power electronics becomes crucial with the next generation of SiC devices. This paper shows that the existing layout of a railway inverter, operating with Si IGBTs already exhibits a dynamic current imbalance between paralleled modules. This will not allow using this geometry with SiC MOSFETs. A complete investigation of the electromagnetic origin of this issue has been performed. A generic circuit model has been proposed to establish a cabling rule to design a Gate Distribution Printed Circuit Board (PCB) in such a way that it compensates the power dissymmetry. An optimization strategy has been used to obtain a new geometry of this PCB, which has been validated with a time domain simulation.

Keywords: power electronics; PEEC method; optimization; paralleling devices; 3D layout; stray inductance; coupling (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2021
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