Developing a TEI-Aware PMIC for Ultra-Low-Power System-on-Chips

Kyu-Bae Lee, Jina Park, Eunjin Choi, Mingi Jeon and Woojoo Lee ()
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Kyu-Bae Lee: School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06974, Korea
Jina Park: School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06974, Korea
Eunjin Choi: School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06974, Korea
Mingi Jeon: School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06974, Korea
Woojoo Lee: School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06974, Korea

Energies, 2022, vol. 15, issue 18, 1-12

Abstract: As the demand for ultra-low-power (ULP) devices has increased tremendously, system-on-chip (SoC) designs based on ultra-low-voltage (ULV) operation have been receiving great attention. Moreover, research has shown the remarkable potential that even more power savings can be achieved in ULV SoCs by exploiting the temperature effect inversion (TEI) phenomenon, i.e., the delay of the ULV SoCs decreases with increasing temperature. However, TEI-aware low-power (TEI-LP) techniques have a critical limitation in practical terms, in that dedicated power management-integrated circuits (PMICs) have not yet been developed. In other words, it is essential to develop PMICs that automatically bring out the full potential of the TEI-LP techniques as the chip temperature changes. With the aim of designing such PMICs, this paper first conducted a study to find the most suitable DC-DC converter for PMICs and then developed a control algorithm to maximize the effectiveness of the TEI-LP techniques. Furthermore, we have developed a compact hardware controller for the algorithm to operate most energy efficiently on ULP-SoCs.

Keywords: PMIC; system-on-chip; temperature effect inversion; ultra-low-power (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2022
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