Design of a Gate-Driving Cell for Enabling Extended SiC MOSFET Voltage Blocking

Walid Issa (), Jose Ortiz Gonzalez and Olayiwola Alatise
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Walid Issa: Electrical Engineering Department, Sheffield Hallam University, Sheffield S1 1WB, UK
Jose Ortiz Gonzalez: School of Engineering, University of Warwick, Coventry CV4 7AL, UK
Olayiwola Alatise: School of Engineering, University of Warwick, Coventry CV4 7AL, UK

Energies, 2022, vol. 15, issue 20, 1-20

Abstract: A series connection of SiC MOSFETs for kV blocking capability can enable more design flexibility in modular multi-level converters as well as other topologies. In this paper, a novel gate driver circuit capable of driving series-connected SiC MOSFETs for high voltage applications is proposed. The primary advantage of the proposed design is that a single gate driver was used to switch all the series devices. The circuit used switching capacitors to sequentially charge and discharge device gate capacitances during switching and enable a negative turn-off voltage to avoid device coupling from Miller-capacitive feedback effects. With the proposed gate driver design and appropriate component values selection, avalanche breakdown due to voltage divergence during switching transients could be avoided with only a minor imbalance in the top device. Simulations and experimental measurements showed that the zero-current turn-off transition of all switches was achieved, and this approved the validity of the design.

Keywords: series SiC MOSFET; driving circuit; high voltage (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2022
References: View complete reference list from CitEc
Citations: View citations in EconPapers (1)

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