Analytical Model and Design of Voltage Balancing Parameters of Series-Connected SiC MOSFETs Considering Non-Flat Miller Plateau of Gate Voltage

Chengmin Li, Runtian Chen, Saizhen Chen, Chushan Li, Haoze Luo, Wuhua Li and Xiangning He
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Chengmin Li: College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China
Runtian Chen: College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China
Saizhen Chen: College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China
Chushan Li: University of Illinois at Urbana—Champaign Institute, Zhejiang University, Hangzhou 310027, China
Haoze Luo: College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China
Wuhua Li: College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China
Xiangning He: College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China

Energies, 2022, vol. 15, issue 5, 1-17

Abstract: Series connection is an attractive approach to increase the blocking voltage of SiC power MOSFETs. Currently, the voltage balancing design of the series connection of the SiC MOSFETs highly relies on offline calibration and is challenging in the complex field operation. In this paper, a quantitative model to assess the voltage balancing performance is proposed to achieve a clear mathematical interpretation of the dynamic response of the voltage imbalance control loop. To begin with, an analytical model of the drain-source voltage rising time during the turn-off transient concerning the non-constant Miller plateau is proposed. Based on the turn-off model of the single device, the voltage imbalance sensitivity (VIS) is proposed to describe the influence of the parameters on the gate driving signals on the voltage imbalance. The VIS parameter can be easily achieved from the behavior of single devices, abandoning the complex variables in series connection. Further, for the typical case, active time delay voltage balancing methods are selected to demonstrate the application of the VIS analysis method. Based on VIS, the accurate close-loop design is proposed for controlling the delayed time among the devices. The proposed analysis and method are verified in simulation and experiment. The paper offers a generalized approach to assess the performance and the design of the series connection of the SiC MOSFETs, which can be further applied in many other methods for parameter design and engineering applications.

Keywords: voltage balancing; SiC power MOSFETs; analytical model; active time delay control (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2022
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