A Low Common-Mode SVPWM for Two-Level Three-Phase Voltage Source Inverters

Jian Zheng, Cunxing Peng, Kaihui Zhao () and Mingcheng Lyu
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Jian Zheng: College of Electrical and Information Engineering, Hunan University of Technology, Zhuzhou 412007, China
Cunxing Peng: College of Electrical and Information Engineering, Hunan University of Technology, Zhuzhou 412007, China
Kaihui Zhao: College of Electrical and Information Engineering, Hunan University of Technology, Zhuzhou 412007, China
Mingcheng Lyu: College of Electrical and Information Engineering, Hunan University, Changsha 410082, China

Energies, 2023, vol. 16, issue 21, 1-17

Abstract: In order to reduce the common-mode voltage (CMV) generated by the use of space vector pulse width modulation (SVPWM) in two-level three-phase voltage source inverters, a low common-mode SVPWM method is proposed. In this method, the voltage plane is divided into 12 sectors, and on each sector, two non-zero vectors of the same class and one single zero vector are adopted for synthesis. The action time of the zero vector is placed at both ends of each switching cycle, the currents are sampled at the beginning of each switching cycle, and the action time and sequence of vectors on each sector is provided. Simulation and experimental results show that, in the vector control system of a permanent magnet synchronous motor fed by the inverter, compared with the conventional SVPWM, the proposed method reduces the CMV peak-to-valley value by 33.333%, the CMV jump frequency by three times, and the performance of the line voltage and line current. The electromagnetic torque and rotor speed remain good, which has good application value in high-performance drives.

Keywords: voltage source inverter; space vector; pulse width modulation; common-mode voltage (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2023
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