Mixed Riccati–Lyapunov Balanced Truncation for Order Reduction of Electrical Circuit Systems

Huy-Du Dao, Thanh-Tung Nguyen (), Ngoc-Kien Vu (), Hong-Son Vu and Hong-Quang Nguyen ()
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Huy-Du Dao: Faculty of Electronics, Thai Nguyen University of Technology, Thai Nguyen 251750, Vietnam
Thanh-Tung Nguyen: Faculty of Engineering and Technology, Thai Nguyen University of Information and Communication Technology, Thai Nguyen 250000, Vietnam
Ngoc-Kien Vu: Research Development Institute of Advanced Industrial Technology (RIAT), Thai Nguyen University of Technology, Thai Nguyen 251750, Vietnam
Hong-Son Vu: Faculty of Electronics and Electrical Engineering, Hung Yen University of Technology and Education, Hung Yen 160000, Vietnam
Hong-Quang Nguyen: Faculty of Mechanical, Electrical, Electronics Technology, Thai Nguyen University of Technology, Thai Nguyen 251750, Vietnam

Energies, 2024, vol. 17, issue 11, 1-17

Abstract: This paper proposes a novel algorithm, termed Mixed Riccati–Lyapunov Balanced Truncation (MRLBT), tailored for order reduction of Linear Time-Invariant Continuous-Time Descriptor Systems (LTI-CTD), commonly encountered in electrical and electronic circuit modeling. The MRLBT approach synergistically combines the advantages of balanced truncation (BT) and positive-real balanced truncation (PRBT) techniques while mitigating their limitations. Unlike BT, which preserves stability but not passivity, and PRBT, which retains passivity at the expense of larger reduction errors, MRLBT ensures the preservation of both stability and passivity inherent in the original system. Additionally, MRLBT achieves reduced computational complexity and minimized order reduction errors compared to PRBT. The proposed algorithm transforms the system into an equivalent Mixed Riccati–Lyapunov Balanced form, enabling the construction of a reduced-order model that retains the critical physical properties. Theoretical analysis and proofs are provided, establishing an upper bound on the global order reduction error. The efficacy of MRLBT is demonstrated through a numerical example involving an RLC ladder network, showcasing its superior performance over BT and PRBT in terms of reduced errors in the time and frequency domains.

Keywords: model order reduction; positive-real balanced truncation; balanced truncation; electrical circuit systems; passivity preservation (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2024
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