Test Methodology for Short-Circuit Assessment and Safe Operation Identification for Power SiC MOSFETs

Joao Oliveira (), Jean-Michel Reynes, Hervé Morel, Pascal Frey, Olivier Perrotin, Laurence Allirand, Stéphane Azzopardi, Michel Piton and Fabio Coccetti
Additional contact information
Joao Oliveira: IRT Saint Exupery, CS34436, 3 Rue Tarfaya, 31400 Toulouse, France
Jean-Michel Reynes: IRT Saint Exupery, CS34436, 3 Rue Tarfaya, 31400 Toulouse, France
Hervé Morel: CNRS, INSA Lyon, Université Claude Bernard Lyon 1, Ecole Centrale de Lyon, Ampère, UMR5005, 69621 Villeurbanne, France
Pascal Frey: IRT Saint Exupery, CS34436, 3 Rue Tarfaya, 31400 Toulouse, France
Olivier Perrotin: IRT Saint Exupery, CS34436, 3 Rue Tarfaya, 31400 Toulouse, France
Laurence Allirand: IRT Saint Exupery, CS34436, 3 Rue Tarfaya, 31400 Toulouse, France
Stéphane Azzopardi: IRT Saint Exupery, CS34436, 3 Rue Tarfaya, 31400 Toulouse, France
Michel Piton: IRT Saint Exupery, CS34436, 3 Rue Tarfaya, 31400 Toulouse, France
Fabio Coccetti: IRT Saint Exupery, CS34436, 3 Rue Tarfaya, 31400 Toulouse, France

Energies, 2024, vol. 17, issue 21, 1-20

Abstract: The short-circuit (SC) immunity of power silicon carbide (SiC) MOSFETs is critical for high-reliability applications, where robust monitoring and protection strategies are essential to ensure system safety. Despite their superior voltage blocking capabilities and high energy efficiency, SiC MOSFETs exhibit greater sensitivity to SC-induced degradation compared to their silicon counterparts. This increased vulnerability necessitates the precise assessment of the key SC performance metrics, such as short-circuit withstand time ( T S C W T ), as well as a deeper understanding of the failure mechanisms. In this study, a comprehensive experimental methodology for evaluating the SC behavior of SiC MOSFETs is presented and validated using industrial references. The investigation further explores the concept of a Safe Operating Area (SOA) under SC conditions, highlighting the significant impact of quasi-simultaneous SC events on device lifetime. Additionally, an application case study demonstrates how these events can drastically reduce the device’s lifespan.

Keywords: SiC MOSFET; short circuit; test methodology; failure analysis (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2024
References: View complete reference list from CitEc
Citations:

Downloads: (external link)
https://www.mdpi.com/1996-1073/17/21/5476/pdf (application/pdf)
https://www.mdpi.com/1996-1073/17/21/5476/ (text/html)

Related works:
This item may be available elsewhere in EconPapers: Search for items with the same title.

Export reference: BibTeX RIS (EndNote, ProCite, RefMan) HTML/Text

Persistent link: https://EconPapers.repec.org/RePEc:gam:jeners:v:17:y:2024:i:21:p:5476-:d:1512169

Access Statistics for this article

Energies is currently edited by Ms. Agatha Cao

More articles in Energies from MDPI
Bibliographic data for series maintained by MDPI Indexing Manager ().