Evaluation of an Infinite-Level Inverter Operation Powered by a DC–DC Converter in Open and Closed Loop

Nataly Gabriela Valencia Pavón (), Alexander Aguila Téllez, Javier Rojas Urbano (), Víctor Taramuel Obando and Edwin Guanga
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Nataly Gabriela Valencia Pavón: Faculty of Computer Science and Electronics, Escuela Superior Politécnica de Chimborazo (ESPOCH), Riobamba 060155, Ecuador
Alexander Aguila Téllez: Electrical Engineering Career, Universidad Politécnica Salesiana, Quito 170525, Ecuador
Javier Rojas Urbano: Faculty of Computer Science and Electronics, Escuela Superior Politécnica de Chimborazo (ESPOCH), Riobamba 060155, Ecuador
Víctor Taramuel Obando: Electrical Engineering Career, Universidad Politécnica Salesiana, Quito 170525, Ecuador
Edwin Guanga: Faculty of Computer Science and Electronics, Escuela Superior Politécnica de Chimborazo (ESPOCH), Riobamba 060155, Ecuador

Energies, 2024, vol. 17, issue 22, 1-16

Abstract: This paper evaluates the open- and closed-loop DC–DC converter operation within a DC coupling multilevel inverter architecture to obtain an infinite-level stepped sinusoidal voltage. Adding a cascade controller to the DC–DC converter should reduce the settling time and increase the number of levels in the output voltage waveform; it could decrease the speed error and phase shift concerning the sinusoidal reference signal. The proposed methodology consists of implementing an experimental multilevel inverter with DC coupling through a single-phase bridge inverter energized from a BUCK converter. Trigger signals for the two converters are obtained from a control circuit based in an ATMEGA644P microcontroller to explore its capabilities in power electronics applications. A digital controller is also implemented to evaluate the operation of the BUCK converter in open and closed loop and observe its influence in the stepped sinusoidal output voltage. The evaluation is performed to energize a resistive load with common output voltage in multilevel inverters, i.e., 3, 5, 7, 11, and infinity levels. Results show that during the design stage, fast dynamic elements, like the storage capacitor, can be used to obtain a minimum THD because the settling time is sufficiently fast, the speed error remains small, and there is no need for a controller. A digital controller requires processing time, and although in theory it can reduce the settling time to a minimum, the processor introduces latency in the control signals generation, producing the opposite effect. Controller complexity of the digital controller must be considered because it increases processing time and influences the efficiency of the closed-loop operation.

Keywords: multilevel inverter; infinite-level inverter; BUCK converter; open loop; closed loop (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2024
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