Field Plate Integration for Mitigating Partial Discharge Activity in PCB-Embedded Power Electronic Modules

Paul Bruyere, Eric Vagnon and Yvan Avenas ()
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Paul Bruyere: Université Grenoble Alpes, CNRS, Grenoble INP, G2Elab, 38000 Grenoble, France
Eric Vagnon: Universite Claude Bernard Lyon 1, INSA Lyon, CNRS, Ecole Centrale de Lyon, Ampère, UMR5005, 69130 Ecully, France
Yvan Avenas: Université Grenoble Alpes, CNRS, Grenoble INP, G2Elab, 38000 Grenoble, France

Energies, 2024, vol. 17, issue 9, 1-20

Abstract: This paper proposes a concept based on field plate (FP) integration inside printed circuit board (PCB)-embedded power modules. The goal is to reduce the electric field at their surface and thus increase the partial discharge inception voltage (PDIV). Electrostatic simulations are first carried out to analyze the electric field reduction induced by the use of FPs. Then, dedicated experiments are proposed to demonstrate that the actual PDIV increases in AC sinus 50 Hz when FPs are implemented. More specifically, it is observed that an optimal FP length exists. Several analyses based on simulations and experiments are thus proposed to explain this phenomenon. Finally, an assessment of PD activity and PD location is presented to support the analysis. AC sinus 50 Hz characterizations indicate that PDIV can be increased by 178% compared to PCBs without FPs with a proper definition of equipotential prolongation and PCB length.

Keywords: PCB embedding; numerical simulations; AC partial discharge characterization; AC partial discharge localization (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2024
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