GaN Power Transistors in Converter Design Techniques

Piotr J. Chrzan () and Pawel B. Derkacz
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Piotr J. Chrzan: Faculty of Electrical and Control Engineering, Gdańsk University of Technology, 80-233 Gdańsk, Poland
Pawel B. Derkacz: Arex—(WB Group), Hutnicza 3, 81-212 Gdynia, Poland

Energies, 2025, vol. 18, issue 11, 1-16

Abstract: The expected outstanding performance of GaN-based transistors in power applications, characterized by high switching frequency, efficiency, and compactness, requires that the design rules of converter layout optimization, filtering, and shielding need to be reexamined. Addressing the above topics, this paper reviews commercial GaN power transistors and specifies their integration techniques, including printed circuit board (PCB) embedded solutions. Then, referring to the optimization results of a half-bridge inverter leg, design techniques are presented that reduce the harmful effect of inductive and capacitive internal converter couplings, thus mitigating the electromagnetic interference (EMI) conducted emissions.

Keywords: gallium nitride (GaN) power transistor; EMI mitigation; PCB layout optimization; PCB embedding technology; half-bridge inverter (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2025
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