C OSS Losses in Resonant Converters

Giuseppe Samperi, Antonio Laudani, Nunzio Salerno, Alfio Scuto, Marco Ventimiglia and Santi Agatino Rizzo ()
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Giuseppe Samperi: Department of Electrical Electronic and Computer Engineering (DIEEI), University of Catania, 95125 Catania, Italy
Antonio Laudani: Department of Electrical Electronic and Computer Engineering (DIEEI), University of Catania, 95125 Catania, Italy
Nunzio Salerno: Department of Electrical Electronic and Computer Engineering (DIEEI), University of Catania, 95125 Catania, Italy
Alfio Scuto: ST Microelectronics S.r.l., 95121 Catania, Italy
Marco Ventimiglia: ST Microelectronics S.r.l., 95121 Catania, Italy
Santi Agatino Rizzo: Department of Electrical Electronic and Computer Engineering (DIEEI), University of Catania, 95125 Catania, Italy

Energies, 2025, vol. 18, issue 13, 1-29

Abstract: High efficiency and high power density are key targets in modern power conversion. Operating power converters at high switching frequencies enables the use of smaller passive components, which, in turn, facilitate achieving high power density. However, the concurrent increase in switching frequency and power density leads to efficiency and overheating issues. Soft switching techniques are typically employed to minimize switching losses and significantly improve efficiency by reducing power losses. However, the hysteresis behavior of the power electronics devices’ output capacitance, C OSS , is the cause of regrettable losses in Super-Junction (SJ) MOSFETs, SiC MOSFETs, and GaN HEMTs, which are usually adopted in soft switching-based conversion schemes. This paper reviews the techniques for measuring hysteresis traces and power losses, as well as the understanding of the phenomenon to identify current research trends and open problems. A few studies have reported that GaN HEMTs tend to exhibit the lowest hysteresis losses, while Si superjunction (SJ) MOSFETs often show the highest. However, this conclusion cannot be generalized by comparing the results from different works because they are typically made across devices with different (when the information is reported) breakdown voltages, on-state resistances, die sizes, and test conditions. Moreover, some recent investigations using advanced TCAD simulations have demonstrated that newer Si-SJ MOSFETs employing trench-filling epitaxial growth can achieve significantly reduced hysteresis losses. Similarly, while multiple studies confirm that hysteresis losses increase with increasing dv/dt and decreasing temperature, the extent of this dependence varies significantly with device structure and test methodology. This difficulty in obtaining a general conclusion is due to the lack of proper figures of merit that account for hysteresis losses, making it problematic to evaluate the suitability of different devices in resonant converters. This problem highlights the primary current challenge, which is the development of a standard and automated method for characterizing C OSS hysteresis. Consequently, significant research effort must be invested in addressing this main challenge and the other challenges described in this study to enable power electronics researchers and practitioners to develop resonant converters properly.

Keywords: efficiency; power electronics; resonant converter; superjunction MOSFET; wide-bandgap devices; zero voltage switching (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2025
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