Design and Performance Analysis of a Platform-Based Multi-Phase Interleaved Synchronous Buck Converter

Mario A. Trape (), Ali Hellany, Jamal Rizk and Mahmood Nagrial
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Mario A. Trape: School of Engineering, Design and Built Environment, Western Sydney University, Sydney, NSW 2747, Australia
Ali Hellany: School of Engineering, Design and Built Environment, Western Sydney University, Sydney, NSW 2747, Australia
Jamal Rizk: School of Engineering, Design and Built Environment, Western Sydney University, Sydney, NSW 2747, Australia
Mahmood Nagrial: School of Engineering, Design and Built Environment, Western Sydney University, Sydney, NSW 2747, Australia

Energies, 2025, vol. 18, issue 3, 1-29

Abstract: This paper proposes a design for a platform-based Multi-phase Interleaved Synchronous Buck Converter (MISBC). A custom platform was developed to compare the theoretical performance of a MISBC circuit simulated with Multisim to a prototype that was built at Western Sydney University. The work disclosed in this manuscript describes some steps adopted during the selection of each component and technical considerations taken during the design of the Printed Circuit Board (PCB). The platform designed has a maximum power output of 260 Watts, with a buck reduction of the nominal voltage from 97 Volts to 24 Volts at a maximum switching frequency of 50 kHz. This switching frequency is achieved with an open-loop circuit configuration coupled with synchronized signal generators, used to validate the dead band required between the activation of each set of transistors implemented in a half-bridge configuration. A summary of the results based on the duty cycle required to achieve the buck voltage desired highlights the advantages of each operating mode of the MISBC circuit. Here the theoretical performance is compared against the data acquired during functional evaluations of the prototype, making possible future interpretations of the ideal control algorithm required to maximize the performance output of MISBC circuits.

Keywords: DC-DC Converter; Buck Converter; GaN FET; Power Electronics; Circuit Design (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2025
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