Low-Power Energy-Efficient Hetero-Dielectric Gate-All-Around MOSFETs: Enablers for Sustainable Smart City Technology

Ram Devi, Gurpurneet Kaur (), Ameeta Seehra, Munish Rattan, Geetika Aggarwal and Michael Short ()
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Ram Devi: Department of Electronics and Communication Engineering, National Institute of Technical Teachers Training and Research, Chandigarh 160019, India
Gurpurneet Kaur: Department of Electronics and Communication Engineering, Guru Nanak Dev Engineering College, Ludhiana 141006, India
Ameeta Seehra: Department of Electronics and Communication Engineering, Guru Nanak Dev Engineering College, Ludhiana 141006, India
Munish Rattan: Department of Electronics and Communication Engineering, Guru Nanak Dev Engineering College, Ludhiana 141006, India
Geetika Aggarwal: Department of Engineering, School of Computing Engineering and Digital Technologies Teesside University, Middlesbrough TS1 3BX, UK
Michael Short: Department of Engineering, School of Computing Engineering and Digital Technologies Teesside University, Middlesbrough TS1 3BX, UK

Energies, 2025, vol. 18, issue 6, 1-21

Abstract: In the context of increasing digitalization and the emergence of applications such as smart cities, embedded devices are becoming ever more pervasive, mobile, and ubiquitous. Due to increasing concerns around energy efficiency, gate density, and scalability in the semiconductor industry, there has been much interest recently in the fabrication of viable low-power energy-efficient devices. The Hetero-Dielectric Gate-All-Around (HD-GAA) MOSFET represents a cutting-edge transistor architecture designed for superior sustainability and energy efficiency, improving the overall efficiency of the system by reducing leakage and enhancing gate control; therefore, as part of the transition to a sustainable future, several semiconductor industries, including Intel, Samsung, Texas Instruments, and IBM, are using this technology. In this study, Hetero-Dielectric Single-Metal Gate-All-Around MOSFET (HD-SM-GAA MOSFET) devices and circuits were designed using Schottky source/drain contacts and tunable high-k dielectric Hf x Ti 1−x O 2 in the TCAD simulator using the following specifications: N-Channel HD-SM-GAA MOSFET (‘Device-I’) with a 5 nm radius and a 21 nm channel length alongside two P-Channel HD-SM-GAA MOSFETs (‘Device-II’ and ‘Device-III’) with radii of 5 nm and 8 nm, respectively, maintaining the same channel length. Thereafter, the inverters were implemented using these devices in the COGENDA TCAD simulator. The results demonstrated significant reductions in short-channel effects: subthreshold swing (SS) (‘Device-I’ = 61.5 mV/dec, ‘Device-II’ = 61.8 mV/dec) and drain-induced barrier lowering (DIBL) (‘Device-I’ = 8.2 mV/V, ‘Device-II’ = 8.0 mV/V) in comparison to the existing literature. Furthermore, the optimized inverters demonstrated significant improvements in noise margin values such as Noise Margin High (NM H ) and Noise Margin Low (NM L ), with Inverter-1 showing 38% and 44% enhancements and Inverter-2 showing 40% and 37% enhancements, respectively, compared to the existing literature. The results achieved illustrate the potential of using this technology (e.g., for power inverters) in embedded power control applications where energy efficiency and scalability are important, such as sustainable smart cities.

Keywords: low-power energy-efficient inverter; high k; gate all around (GAA); Schottky contact; metal-oxide field-effect transistor (MOSFET); smart cities; sustainability (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2025
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