A High Performance Real-Time Simulator for Controllers Hardware-in-the-Loop Testing

Mahmoud Matar, Houshang Karimi, Amir Etemadi and Reza Iravani
Additional contact information
Mahmoud Matar: University of Toronto, Toronto, ON, M5S 3G4, Canada
Houshang Karimi: Sharif University of Technology, Tehran, P.O. Box 11365-9363, Iran
Amir Etemadi: University of Toronto, Toronto, ON, M5S 3G4, Canada
Reza Iravani: University of Toronto, Toronto, ON, M5S 3G4, Canada

Energies, 2012, vol. 5, issue 6, 1-21

Abstract: This paper presents a high performance real-time simulator for power electronic systems applications and primarily intended for controller hardware-in-the-loop (CHIL) testing. The novelty of the proposed simulator resides in the massively parallel hardware architecture that efficiently exploits fine-grained parallelism without imposing severe communication overhead time that can limit the performance. The simulator enables the use of a nanosecond range simulation timestep to simulate power electronic systems. Through the use of this nanosecond range simulation timestep, the simulator minimizes the error arising from the intersimulation timestep switching phenomenon associated with CHIL. The proposed hardware architecture is realized based on the FPGA technology. The simulator is tested and its CHIL capability verified based on the closed-loop testing of a robust multivariable servomechanism controller for autonomous operation of a distributed generation unit.

Keywords: real-time simulation; electromagnetic transients; distributed generation; power electronics interface; modeling; FPGA (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2012
References: View references in EconPapers View complete reference list from CitEc
Citations: View citations in EconPapers (5)

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