Integrating Physical Unclonable Functions with Machine Learning for the Authentication of Edge Devices in IoT Networks

Abdul Manan Sheikh (), Md. Rafiqul Islam, Mohamed Hadi Habaebi (), Suriza Ahmad Zabidi, Athaur Rahman Bin Najeeb and Adnan Kabbani
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Abdul Manan Sheikh: Department of Electrical Engineering and Computer Science, College of Engineering, A’Sharqiyah University, Ibra 400, Oman
Md. Rafiqul Islam: Department of Electrical Computer Engineering, Kulliyyah of Engineering, International Islamic University, Kuala Lumpur 53100, Malaysia
Mohamed Hadi Habaebi: Department of Electrical Computer Engineering, Kulliyyah of Engineering, International Islamic University, Kuala Lumpur 53100, Malaysia
Suriza Ahmad Zabidi: Department of Electrical Computer Engineering, Kulliyyah of Engineering, International Islamic University, Kuala Lumpur 53100, Malaysia
Athaur Rahman Bin Najeeb: Department of Electrical Computer Engineering, Kulliyyah of Engineering, International Islamic University, Kuala Lumpur 53100, Malaysia
Adnan Kabbani: Department of Electrical Engineering and Computer Science, College of Engineering, A’Sharqiyah University, Ibra 400, Oman

Future Internet, 2025, vol. 17, issue 7, 1-35

Abstract: Edge computing (EC) faces unique security threats due to its distributed architecture, resource-constrained devices, and diverse applications, making it vulnerable to data breaches, malware infiltration, and device compromise. The mitigation strategies against EC data security threats include encryption, secure authentication, regular updates, tamper-resistant hardware, and lightweight security protocols. Physical Unclonable Functions (PUFs) are digital fingerprints for device authentication that enhance interconnected devices’ security due to their cryptographic characteristics. PUFs produce output responses against challenge inputs based on the physical structure and intrinsic manufacturing variations of an integrated circuit (IC). These challenge-response pairs (CRPs) enable secure and reliable device authentication. Our work implements the Arbiter PUF (APUF) on Altera Cyclone IV FPGAs installed on the ALINX AX4010 board. The proposed APUF has achieved performance metrics of 49.28% uniqueness, 38.6% uniformity, and 89.19% reliability. The robustness of the proposed APUF against machine learning (ML)-based modeling attacks is tested using supervised Support Vector Machines (SVMs), logistic regression (LR), and an ensemble of gradient boosting (GB) models. These ML models were trained over more than 19K CRPs, achieving prediction accuracies of 61.1%, 63.5%, and 63%, respectively, thus cementing the resiliency of the device against modeling attacks. However, the proposed APUF exhibited its vulnerability to Multi-Layer Perceptron (MLP) and random forest (RF) modeling attacks, with 95.4% and 95.9% prediction accuracies, gaining successful authentication. APUFs are well-suited for device authentication due to their lightweight design and can produce a vast number of challenge-response pairs (CRPs), even in environments with limited resources. Our findings confirm that our approach effectively resists widely recognized attack methods to model PUFs.

Keywords: edge computing; physical unclonable functions; challenge-response pairs; machine learning; support vector machine; logistic regression; multi-layer perceptron (search for similar items in EconPapers)
JEL-codes: O3 (search for similar items in EconPapers)
Date: 2025
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