Evolutionary Synthesis of Failure-Resilient Analog Circuits
Žiga Rojec,
Iztok Fajfar and
Árpád Burmen
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Žiga Rojec: Faculty of Electrical Engineering, University of Ljubljana, Tržaška cesta 25, SI-1000 Ljubljana, Slovenia
Iztok Fajfar: Faculty of Electrical Engineering, University of Ljubljana, Tržaška cesta 25, SI-1000 Ljubljana, Slovenia
Árpád Burmen: Faculty of Electrical Engineering, University of Ljubljana, Tržaška cesta 25, SI-1000 Ljubljana, Slovenia
Mathematics, 2022, vol. 10, issue 1, 1-20
Abstract:
Analog circuit design requires large amounts of human knowledge. A special case of circuit design is the synthesis of robust and failure-resilient electronics. Evolutionary algorithms can aid designers in exploring topologies with new properties. Here, we show how to encode a circuit topology with an upper-triangular incident matrix and use the NSGA-II algorithm to find computational circuits that are robust to component failure. Techniques for robustness evaluation and evolutionary algorithm guidances are described. As a result, we evolve square root and natural logarithm computational circuits that are robust to high-impedance or short-circuit malfunction of an arbitrary rectifying diode. We confirm the simulation results by hardware circuit implementation and measurements. We think that our research will inspire further searches for failure-resilient topologies.
Keywords: evolutionary algorithms; analog circuit synthesis; failure-resilient circuits; NSGA-II (search for similar items in EconPapers)
JEL-codes: C (search for similar items in EconPapers)
Date: 2022
References: View complete reference list from CitEc
Citations: View citations in EconPapers (2)
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Persistent link: https://EconPapers.repec.org/RePEc:gam:jmathe:v:10:y:2022:i:1:p:156-:d:717962
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