High-Speed Wavelet Image Processing Using the Winograd Method with Downsampling

Pavel Lyakhov, Nataliya Semyonova, Nikolay Nagornov, Maxim Bergerman and Albina Abdulsalyamova ()
Additional contact information
Pavel Lyakhov: Department of Mathematical Modelling, North-Caucasus Federal University, 355009 Stavropol, Russia
Nataliya Semyonova: Department of Mathematical Modelling, North-Caucasus Federal University, 355009 Stavropol, Russia
Nikolay Nagornov: Department of Mathematical Modelling, North-Caucasus Federal University, 355009 Stavropol, Russia
Maxim Bergerman: Department of Mathematical Modelling, North-Caucasus Federal University, 355009 Stavropol, Russia
Albina Abdulsalyamova: Department of Mathematical Modelling, North-Caucasus Federal University, 355009 Stavropol, Russia

Mathematics, 2023, vol. 11, issue 22, 1-10

Abstract: Wavelets are actively used to solve a wide range of image processing problems in various fields of science and technology. Modern image processing systems cannot keep up with the rapid growth in digital visual information. Various approaches are used to reduce the computational complexity and increase computational speeds. The Winograd method (WM) is one of the most promising. However, this method is used to obtain sequential values. Its use for wavelet image processing requires expanding the calculation methodology to cases of downsampling. This paper proposes a new approach to reduce the computational complexity of wavelet image processing based on the WM with decimation. Calculations have been carried out and formulas have been derived that implement digital filtering using the WM with downsampling. The derived formulas can be used for 1D filtering with an arbitrary downsampling stride. Hardware modeling of wavelet image filtering on an FPGA showed that the WM reduces the computational time by up to 66%, with increases in the hardware costs and power consumption of 95% and 344%, respectively, compared to the direct method. A promising direction for further research is the implementation of the developed approach on ASIC and the use of modular computing for more efficient parallelization of calculations and an even greater increase in the device speed.

Keywords: computational complexity; delay reduction; image filtering; decimation; hardware implementation; parallel computing (search for similar items in EconPapers)
JEL-codes: C (search for similar items in EconPapers)
Date: 2023
References: View complete reference list from CitEc
Citations:

Downloads: (external link)
https://www.mdpi.com/2227-7390/11/22/4644/pdf (application/pdf)
https://www.mdpi.com/2227-7390/11/22/4644/ (text/html)

Related works:
This item may be available elsewhere in EconPapers: Search for items with the same title.

Export reference: BibTeX RIS (EndNote, ProCite, RefMan) HTML/Text

Persistent link: https://EconPapers.repec.org/RePEc:gam:jmathe:v:11:y:2023:i:22:p:4644-:d:1279952

Access Statistics for this article

Mathematics is currently edited by Ms. Emma He

More articles in Mathematics from MDPI
Bibliographic data for series maintained by MDPI Indexing Manager ().