Mathematical Circuit Root Simplification Using an Ensemble Heuristic–Metaheuristic Algorithm

Navid Behmanesh-Fard, Hossein Yazdanjouei, Mohammad Shokouhifar () and Frank Werner ()
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Navid Behmanesh-Fard: Department of Electrical Engineering, Technical and Vocational University (TVU), Tehran 1435661137, Iran
Hossein Yazdanjouei: Microelectronics Research Laboratory, Urmia University, Urmia 5756151818, Iran
Mohammad Shokouhifar: Department of Electrical and Computer Engineering, Shahid Beheshti University, Tehran 1983969411, Iran
Frank Werner: Faculty of Mathematics, Otto-Von-Guericke-University, 39016 Magdeburg, Germany

Mathematics, 2023, vol. 11, issue 6, 1-22

Abstract: Symbolic pole/zero analysis is a crucial step in designing an analog operational amplifier. Generally, a simplified symbolic analysis of analog circuits suffers from NP-hardness, i.e., an exponential growth of the number of symbolic terms of the transfer function with the circuit size. This study presents a mathematical model combined with a heuristic–metaheuristic solution method for symbolic pole/zero simplification in operational transconductance amplifiers. First, the circuit is symbolically solved and an improved root splitting method is applied to extract symbolic poles/zeroes from the exact expanded transfer function. Then, a hybrid algorithm based on heuristic information and a metaheuristic technique using simulated annealing is used for the simplification of the derived symbolic roots. The developed method is tested on three operational transconductance amplifiers. The obtained results show the effectiveness of the proposed method in achieving accurate simplified symbolic pole/zero expressions with the least complexity.

Keywords: operational transconductance amplifiers; symbolic circuit analysis; pole/zero extraction; root splitting; simplification; simulated annealing (search for similar items in EconPapers)
JEL-codes: C (search for similar items in EconPapers)
Date: 2023
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