State Feedback with Integral Control Circuit Design of DC-DC Buck-Boost Converter

Humam Al-Baidhani, Abdullah Sahib and Marian K. Kazimierczuk ()
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Humam Al-Baidhani: Department of Electrical Engineering, Wright State University, Dayton, OH 45435, USA
Abdullah Sahib: Department of Electronic and Communication Technologies, Technical Institute, Al-Furat Al-Awsat Technical University, Najaf 54003, Iraq
Marian K. Kazimierczuk: Department of Electrical Engineering, Wright State University, Dayton, OH 45435, USA

Mathematics, 2023, vol. 11, issue 9, 1-18

Abstract: The pulse-with modulated (PWM) dc-dc buck-boost converter is a non-minimum phase system, which requires a proper control scheme to improve the transient response and provide constant output voltage during line and load variations. The pole placement technique has been proposed in the literature to control this type of power converter and achieve the desired response. However, the systematic design procedure of such control law using a low-cost electronic circuit has not been discussed. In this paper, the pole placement via state-feedback with an integral control scheme of inverting the PWM dc-dc buck-boost converter is introduced. The control law is developed based on the linearized power converter model in continuous conduction mode. A detailed design procedure is given to represent the control equation using a simple electronic circuit that is suitable for low-cost commercial applications. The mathematical model of the closed-loop power converter circuit is built and simulated using SIMULINK and Simscape Electrical in MATLAB. The closed-loop dc-dc buck-boost converter is tested under various operating conditions. It is confirmed that the proposed control scheme improves the power converter dynamics, tracks the reference signal, and maintains regulated output voltage during abrupt changes in input voltage and load current. The simulation results show that the line variation of 5 V and load variation of 2 A around the nominal operating point are rejected with a maximum percentage overshoot of 3.5% and a settling time of 5.5 ms.

Keywords: analog control circuit; dc-dc converter; pole placement; pulse-width modulated; state feedback with integral control (search for similar items in EconPapers)
JEL-codes: C (search for similar items in EconPapers)
Date: 2023
References: View references in EconPapers View complete reference list from CitEc
Citations: View citations in EconPapers (2)

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