Building an Analog Circuit Synapse for Deep Learning Neuromorphic Processing

Alejandro Juarez-Lora (), Victor H. Ponce-Ponce (), Humberto Sossa-Azuela, Osvaldo Espinosa-Sosa and Elsa Rubio-Espino
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Alejandro Juarez-Lora: Instituto Politécnico Nacional, Centro de Investigación en Computación, Mexico City 07700, Mexico
Victor H. Ponce-Ponce: Instituto Politécnico Nacional, Centro de Investigación en Computación, Mexico City 07700, Mexico
Humberto Sossa-Azuela: Instituto Politécnico Nacional, Centro de Investigación en Computación, Mexico City 07700, Mexico
Osvaldo Espinosa-Sosa: Instituto Politécnico Nacional, Centro de Investigación en Computación, Mexico City 07700, Mexico
Elsa Rubio-Espino: Instituto Politécnico Nacional, Centro de Investigación en Computación, Mexico City 07700, Mexico

Mathematics, 2024, vol. 12, issue 14, 1-19

Abstract: In this article, we propose a circuit to imitate the behavior of a Reward-Modulated spike-timing-dependent plasticity synapse. When two neurons in adjacent layers produce spikes, each spike modifies the thickness in the shared synapse. As a result, the synapse’s ability to conduct impulses is controlled, leading to an unsupervised learning rule. By introducing a reward signal, reinforcement learning is enabled by redirecting the growth and shrinkage of synapses based on signal feedback from the environment. The proposed synapse manages the convolution of the emitted spike signals to promote either the strengthening or weakening of the synapse, represented as the resistance value of a memristor device. As memristors have a conductance range that may differ from the available current input range of typical CMOS neuron designs, the synapse circuit can be adjusted to regulate the spike’s amplitude current to comply with the neuron. The circuit described in this work allows for the implementation of fully interconnected layers of neuron analog circuits. This is achieved by having each synapse reconform the spike signal, thus removing the burden of providing enough power from the neurons to each memristor. The synapse circuit was tested using a CMOS analog neuron described in the literature. Additionally, the article provides insight into how to properly describe the hysteresis behavior of the memristor in Verilog-A code. The testing and learning capabilities of the synapse circuit are demonstrated in simulation using the Skywater-130 nm process. The article’s main goal is to provide the basic building blocks for deep neural networks relying on spiking neurons and memristors as the basic processing elements to handle spike generation, propagation, and synaptic plasticity.

Keywords: spiking neural networks; analog computing; memristor; crossbar arrays; signal processing (search for similar items in EconPapers)
JEL-codes: C (search for similar items in EconPapers)
Date: 2024
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