Test-Path Scheduling for Interposer-Based 2.5D Integrated Circuits Using an Orthogonal Learning-Based Differential Evolution Algorithm

Chunlei Li, Libao Deng (), Guanyu Yuan, Liyan Qiao, Lili Zhang and Chu Chen
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Chunlei Li: School of Information Science and Engineering, Harbin Institute of Technology, Weihai 264209, China
Libao Deng: School of Information Science and Engineering, Harbin Institute of Technology, Weihai 264209, China
Guanyu Yuan: School of Information Science and Engineering, Harbin Institute of Technology, Weihai 264209, China
Liyan Qiao: School of Electronics and Information Engineering, Harbin Institute of Technology, Harbin 150001, China
Lili Zhang: School of Computing, Dublin City University, D09 V209 Dublin, Ireland
Chu Chen: School of Information Science and Engineering, Harbin Institute of Technology, Weihai 264209, China

Mathematics, 2025, vol. 13, issue 16, 1-30

Abstract: 2.5D integrated circuits (ICs), which utilize an interposer to stack multiple dies side by side, represent a promising architecture for improving system performance, integration density, and design flexibility. However, the complex interconnect structures present significant challenges for post-fabrication testing, especially when scheduling test paths under constrained test access mechanisms. This paper addresses the test-path scheduling problem in interposer-based 2.5D ICs, aiming to minimize both total test time and cumulative inter-die interconnect length. We propose an efficient orthogonal learning-based differential evolution algorithm, named OLELS-DE. The algorithm combines the global optimization capability of differential evolution with an orthogonal learning-based search strategy and an elites local search strategy to enhance the convergence and solution quality. Comprehensive experiments are conducted on a set of benchmark instances with varying die counts, and the proposed method is compared against five state-of-the-art metaheuristic algorithms and CPLEX. Experimental results demonstrate that OLELS-DE consistently outperforms the competitors in terms of test cost reduction and convergence reliability, confirming its robustness and effectiveness for complex test scheduling in 2.5D ICs.

Keywords: 2.5D integrated circuits; test-path scheduling; differential evolution; orthogonal learning (search for similar items in EconPapers)
JEL-codes: C (search for similar items in EconPapers)
Date: 2025
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