Efficient Implementation of ARX-Based Block Ciphers on 8-Bit AVR Microcontrollers

YoungBeom Kim, Hyeokdong Kwon, SangWoo An, Hwajeong Seo and Seog Chung Seo
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YoungBeom Kim: Department of Information Security, Cryptology, and Mathematics, Kookmin University, Seoul 02707, Korea
Hyeokdong Kwon: Division of IT Convergence Engineering, Hansung University, lSeoul 136792, Korea
SangWoo An: Department of Financial Information Security, Kookmin University, Seoul 02707, Korea
Hwajeong Seo: Division of IT Convergence Engineering, Hansung University, lSeoul 136792, Korea
Seog Chung Seo: Department of Information Security, Cryptology, and Mathematics, Kookmin University, Seoul 02707, Korea

Mathematics, 2020, vol. 8, issue 10, 1-22

Abstract: As the development of Internet of Things (IoT), the data exchanged through the network has significantly increased. To secure the sensitive data with user’s personal information, it is necessary to encrypt the transmitted data. Since resource-constrained wireless devices are typically used for IoT services, it is required to optimize the performance of cryptographic algorithms which are computation-intensive tasks. In this paper, we present efficient implementations of ARX-based Korean Block Ciphers (HIGHT and LEA) with CounTeR (CTR) mode of operation, and CTR_DRBG, one of the most widely used DRBGs (Deterministic Random Bit Generators), on 8-bit AVR Microcontrollers (MCUs). Since 8-bit AVR MCUs are widely used for various types of IoT devices, we select it as the target platform in this paper. We present an efficient implementation of HIGHT and LEA by making full use of the property of CTR mode, where the nonce value is fixed, and only the counter value changes during the encryption. On our implementation, the cost of additional function calls occurred by the generation of look-up table can be reduced. With respect to CTR_DRBG, we identified several parts that do not need to be computed. Thus, precomputing those parts in offline and using them online can result in performance improvements for CTR_DRBG. Furthermore, we applied several optimization techniques by making full use of target devices’ characteristics with AVR assembly codes on 8-bit AVR MCUs. Our proposed table generation way can reduce the cost for building a precomputation table by around 6.7% and 9.1% in the case of LEA and HIGHT, respectively. Proposed implementations of LEA and HIGHT with CTR mode on 8-bit AVR MCUs provide 6.3% and 3.8% of improved performance, compared with the previous best results, respectively. Our implementations are the fastest compared to previous LEA and HIGHT implementations on 8-bit AVR MCUs. In addition, the proposed CTR_DRBG implementations on AVR provide better performance by 37.2% and 8.7% when the underlying block cipher is LEA and HIGHT, respectively.

Keywords: LEA block cipher; HIGHT block cipher; counter mode of operation; 8-bit AVR MCUs; CTR_DRBG; random bit; Internet of Things (search for similar items in EconPapers)
JEL-codes: C (search for similar items in EconPapers)
Date: 2020
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