FPGA-Oriented LDPC Decoder for Cyber-Physical Systems

Mateusz Kuc, Wojciech Sułek and Dariusz Kania
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Mateusz Kuc: Institute of Electronics, Silesian University of Technology, ul. Akademicka 2A, 44-100 Gliwice, Poland
Wojciech Sułek: Institute of Electronics, Silesian University of Technology, ul. Akademicka 2A, 44-100 Gliwice, Poland
Dariusz Kania: Institute of Electronics, Silesian University of Technology, ul. Akademicka 2A, 44-100 Gliwice, Poland

Mathematics, 2020, vol. 8, issue 5, 1-15

Abstract: A potentially useful Cyber-Physical Systems element is a modern forward error correction (FEC) coding system, utilizing a code selected from the broad class of Low-Density Parity-Check (LDPC) codes. In this paper, development of a hardware implementation in an FPGAs of the decoder for Quasi-Cyclic (QC-LDPC) subclass of codes is presented. The decoder can be configured to support the typical decoding algorithms: Min-Sum or Normalized Min-Sum (NMS). A novel method of normalization in the NMS algorithm is proposed, one that utilizes combinational logic instead of arithmetic units. A comparison of decoders with different bit-lengths of data (beliefs that are messages propagated between computing units) is also provided. The presented decoder has been implemented with a distributed control system. Experimental studies were conducted using the Intel Cyclone V FPGA module, which is a part of the developed testing environment for LDPC coding systems.

Keywords: cyber physical systems; LDPC; QC-LDPC; FPGA; min-sum; normalized min-sum; distributed control system; token ring (search for similar items in EconPapers)
JEL-codes: C (search for similar items in EconPapers)
Date: 2020
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