Secure HIGHT Implementation on ARM Processors

Hwajeong Seo, Hyunjun Kim, Kyungbae Jang, Hyeokdong Kwon, Minjoo Sim, Gyeongju Song, Siwoo Uhm and Hyunji Kim
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Hwajeong Seo: Division of IT Convergence Engineering, Hansung University, Seoul 02876, Korea
Hyunjun Kim: Division of IT Convergence Engineering, Hansung University, Seoul 02876, Korea
Kyungbae Jang: Division of IT Convergence Engineering, Hansung University, Seoul 02876, Korea
Hyeokdong Kwon: Division of IT Convergence Engineering, Hansung University, Seoul 02876, Korea
Minjoo Sim: Division of IT Convergence Engineering, Hansung University, Seoul 02876, Korea
Gyeongju Song: Division of IT Convergence Engineering, Hansung University, Seoul 02876, Korea
Siwoo Uhm: Division of IT Convergence Engineering, Hansung University, Seoul 02876, Korea
Hyunji Kim: Division of IT Convergence Engineering, Hansung University, Seoul 02876, Korea

Mathematics, 2021, vol. 9, issue 9, 1-12

Abstract: Secure and compact designs of HIGHT block cipher on representative ARM microcontrollers are presented in this paper. We present several optimizations for implementations of the HIGHT block cipher, which exploit different parallel approaches, including task parallelism and data parallelism methods, for high-speed and high-throughput implementations. For the efficient parallel implementation of the HIGHT block cipher, the SIMD instructions of ARM architecture are fully utilized. These instructions support four-way 8-bit operations in the parallel way. The length of primitive operations in the HIGHT block cipher is 8-bit-wise in addition–rotation–exclusive-or operations. In the 32-bit word architecture (i.e., the 32-bit ARM architecture), four 8-bit operations are executed at once with the four-way SIMD instruction. By exploiting the SIMD instruction, three parallel HIGHT implementations are presented, including task-parallel, data-parallel, and task/data-parallel implementations. In terms of the secure implementation, we present a fault injection countermeasure for 32-bit ARM microcontrollers. The implementation ensures the fault detection through the representation of intra-instruction redundancy for the data format. In particular, we proposed two fault detection implementations by using parallel implementations. The two-way task/data-parallel based implementation is secure against fault injection models, including chosen bit pair, random bit, and random byte. The alternative four-way data-parallel-based implementation ensures all security features of the aforementioned secure implementations. Moreover, the instruction skip model is also prevented. The implementation of the HIGHT block cipher is further improved by using the constant value of the counter mode of operation. In particular, the 32-bit nonce value is pre-computed and the intermediate result is directly utilized. Finally, the optimized implementation achieved faster execution timing and security features toward the fault attack than previous works.

Keywords: efficient implementation; ARM Cortex-M4; HIGHT block cipher; fault attack detection (search for similar items in EconPapers)
JEL-codes: C (search for similar items in EconPapers)
Date: 2021
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