Enabling Packet Classification with Low Update Latency for SDN Switch on FPGA

Chenglong Li, Tao Li, Junnan Li, Zilin Shi and Baosheng Wang
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Chenglong Li: Computer College, National University of Defense Technology, Changsha 410073, China
Tao Li: Computer College, National University of Defense Technology, Changsha 410073, China
Junnan Li: Computer College, National University of Defense Technology, Changsha 410073, China
Zilin Shi: Computer College, National University of Defense Technology, Changsha 410073, China
Baosheng Wang: Computer College, National University of Defense Technology, Changsha 410073, China

Sustainability, 2020, vol. 12, issue 8, 1-16

Abstract: Field Programmable Gate Array (FPGA) is widely used in real-time network processing such as Software-Defined Networking (SDN) switch due to high performance and programmability. Bit-Vector (BV)-based approaches can implement high-performance multi-field packet classification, on FPGA, which is the core function of the SDN switch. However, the SDN switch requires not only high performance but also low update latency to avoid controller failure. Unfortunately, the update latency of BV-based approaches is inversely proportional to the number of rules, which means can hardly support the SDN switch effectively. It is reasonable to split the ruleset into sub-rulesets that can be performed in parallel, thereby reducing update latency. We thus present SplitBV for the efficient update by using several distinguishable exact-bits to split the ruleset. SplitBV consists of a constrained recursive algorithm for selecting the bit positions that can minimize the latency and a hybrid lookup pipeline. It can achieve a significant reduction in update latency with negligible memory growth and comparable high performance. We implement SplitBV and evaluate its performance by simulation and FPGA prototype. Experimental results show that our approach can reduce 73% and 36% update latency on average for synthetic 5-tuple rules and OpenFlow rules respectively.

Keywords: SDN switch; Packet Classification; update latency; Bit-Vector; FPGA (search for similar items in EconPapers)
JEL-codes: O13 Q Q0 Q2 Q3 Q5 Q56 (search for similar items in EconPapers)
Date: 2020
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